ARM Cortex-A34
Family of microprocessor cores with ARM microarchitecture
From Wikipedia, the free encyclopedia
The ARM Cortex-A34 is a low power central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Ltd.[1]
| General information | |
|---|---|
| Launched | 2019 |
| Designed by | ARM Holdings |
| Physical specifications | |
| Cores |
|
| Cache | |
| L1 cache | 16–128 KB (8–64 KB I-cache with parity, 8–64 KB D-cache) per core |
| L2 cache | 128–1024 KB |
| L3 cache | No |
| Architecture and classification | |
| Application | Mobile Network Infrastructure Automotive designs Servers |
| Instruction set | ARMv8-A |
| History | |
| Predecessor | ARM Cortex-A32 (32-bit only) |
Licensing
The Cortex-A34 is available as a SIP core to licensees whilst its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).[2]
Technical
| Architecture | 64-bit Armv8-A (AArch64 only) |
| Multicore | Up to 4 core |
| Superscalar | Partial[3] |
| Pipeline | In order (like ARM Cortex-A53 and ARM Cortex-A55) |
| L1 I-Cache / D-Cache | 8k-64k |
| L2 Cache | 128KB-1MB[4] |
| ISA Support | Only AArch64 for 64-bit |
| Debug & Trace | CoreSight SoC-400[2] |
See also
- Comparison of ARMv8-A cores, ARMv8 family
- Comparison of ARMv7-A cores, ARMv7 family