ARM Cortex-A510
ARM microprocessor 'LITTLE' core model
From Wikipedia, the free encyclopedia
The ARM Cortex-A510 is the successor to the ARM Cortex-A55 and the first ARMv9 high efficiency "LITTLE" CPU.[1] It is the companion to the ARM Cortex-A710 "big" core. It is a clean-sheet 64-bit CPU designed by ARM Holdings' Cambridge design team.[2]
| General information | |
|---|---|
| Launched | 2021 |
| Designed by | ARM Ltd. |
| Cache | |
| L1 cache | 64/128 KiB (32/64 KiB I-cache with parity, 32/64 KiB D-cache) per core |
| L2 cache | 0–512 KiB per complex |
| L3 cache | 128 KiB – 16 MiB (optional) |
| Architecture and classification | |
| Microarchitecture | ARM Cortex-A510 |
| Instruction set | ARMv9-A |
| Products, models, variants | |
| Product code name |
|
| Variant | |
| History | |
| Predecessor | ARM Cortex-A55 |
| Successor | ARM Cortex-A520 |
Design
The Cortex-A510 is a “LITTLE” CPU core focusing on high efficiency,[3] bringing the following improvements from last gen:
- 3-wide in-order design, the Cortex-A55 was 2-wide.[4]
- 3-wide fetch and decode front-end as well as 3-wide issue and execute on the back-end, which includes 3 ALU's.[5]
- 35% performance uplift compared to Cortex-A55
- 20% more energy efficient than Cortex-A55
- 3x ML uplift[1]
ARM announced a refresh for the Cortex-A510 CPU core on 28 June 2022 along with other CPU cores.
The refresh improved power efficiency by 5% and scalability from 8 cores to up to 12 cores.[6] Additionally, the refresh could be configured with 32-bit support, whereas the original was 64-bit only.[7]
Architecture comparison
- "LITTLE" core
| uArch | Cortex-A53 | Cortex-A55 | Cortex-A510 | Cortex-A520 |
|---|---|---|---|---|
| Codename | Apollo | Ananke | Klein | Hayes |
| Peak clock speed | 2.3 GHz | 2.1 GHz | 2.0 GHz | 2.0 GHz |
| Architecture | ARMv8.0-A | ARMv8.2-A | ARMv9.0-A | ARMv9.2-A |
| AArch | 32-bit and 64-bit | 64-bit | ||
| Branch predictor history (entries) |
3072[8] | - | ||
| Max In-flight | None (In-order) | |||
| L0 (Mops entries) | None | |||
| L1-I + L1-D | 8/64+8/64 KiB | 16/64+16/64 KiB | 32/64+32/64 KiB | |
| L2 | 0–256 KiB | 0–512 KiB | ||
| L3 | None | 0–4 MiB | 0–16 MiB | 0–32 MiB |
| Decode Width | 2 | 3 | 3 (2 ALU) | |
| Dispatch | 8[9] | |||
Usage
The Cortex-A510 CPU core is used in the following SoCs
- Qualcomm • Snapdragon 8 gen 1[10] • Snapdragon 8+ gen 1[11] • Snapdragon 8 gen 2[12] • Snapdragon 7 gen 1[13] • Snapdragon 7+ gen 2[14]
- MediaTek • Dimensity 9200+[15] • Dimensity 9200[16] • Dimensity 9000+[17] • Dimensity 9000[18] • Dimensity 8300 • Dimensity 7200[19]
- Samsung • Exynos 2200[20]
- HiSilicon • Kirin 9000S[21]
- Google • Tensor G3[22]