ARM Cortex-A520

High-efficiency CPU core design From Wikipedia, the free encyclopedia

The ARM Cortex-A520 is a "little" CPU core model from Arm[1] unveiled in TCS23 (total compute solution). It serves as a successor to the CPU core ARM Cortex-A510.[2] The Cortex-A5xx CPU cores series generally focus on high efficiency, the CPU core can be paired with the other CPU cores in its family like ARM Cortex-A720 or/and Cortex-X4 in a CPU cluster.[3]

Launched2023
Designed byARM Ltd.
Max. CPU clock rate1.8 GHz  to 2.27 GHz 
L1 cache64/128 KiB
(32/64 KiB I-cache with parity,
32/64 KiB D-cache) per core
Quick facts General information, Launched ...
ARM Cortex-A520
General information
Launched2023
Designed byARM Ltd.
Performance
Max. CPU clock rate1.8 GHz  to 2.27 GHz 
Cache
L1 cache64/128 KiB
(32/64 KiB I-cache with parity,
32/64 KiB D-cache) per core
L2 cache0–512 KiB per complex
L3 cache256 KiB – 32 MiB (optional)
Architecture and classification
MicroarchitectureARM Cortex-A520
Instruction setARMv9.2-A
Products, models, variants
Product code name
  • Hayes
History
PredecessorARM Cortex-A510
SuccessorARM C1-Nano
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Improvements

  • 8% peak performance improvement over the Cortex-A510[4]
  • Support only 64-bit applications
  • Up to 512 KiB of private L2 cache (From 256 KiB)
  • Add QARMA3 Pointer Authentication (PAC) algorithm support
  • Update to ARMv9.2[5]

Architecture comparison

"LITTLE" core
More information uArch, Cortex-A53 ...
uArch Cortex-A53 Cortex-A55 Cortex-A510 Cortex-A520
Codename Apollo Ananke Klein Hayes
Peak clock speed 2.3 GHz 2.1 GHz 2.0 GHz 2.0 GHz
Architecture ARMv8.0-A ARMv8.2-A ARMv9.0-A ARMv9.2-A
AArch 32-bit and 64-bit 64-bit
Branch predictor
history (entries)		 3072[6] -
Max In-flight None (In-order)
L0 (Mops entries) None
L1-I + L1-D 8/64+8/64 KiB 16/64+16/64 KiB 32/64+32/64 KiB
L2 0–256 KiB 0–512 KiB
L3 None 0–4 MiB 0–16 MiB 0–32 MiB
Decode Width 2 3 3 (2 ALU)
Dispatch 8[7]
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See also

References

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