ARM Cortex-A715

ARM Cortex-A715
General information
Launched	2022
Designed by	ARM Ltd.
Cache
L1 cache	64/128 KiB ; (32/64 KiB I-cache with parity, ; 32/64 KiB D-cache) per core
L2 cache	128–512 KiB per core
L3 cache	256 KiB – 16 MiB (optional)
Architecture and classification
Microarchitecture	ARM Cortex-A715
Instruction set	ARMv9.0-A
Products, models, variants
Product code name	Makalu;
Variant	ARM Cortex-X3;
History
Predecessor	ARM Cortex-A710
Successor	ARM Cortex-A720

The ARM Cortex-A715 is the second generation ARMv9 "big" Cortex CPU.^[1] Compared to its predecessor the Cortex-A710 the Cortex-A715 CPU is noted for having a 20% increase in power efficiency, and 5% improvement in performance.^[1] The Cortex-A715 shows comparable performance to the previous generation Cortex-X1 CPU.^[2]^[3]

Launched2022

Designed byARM Ltd.

L1 cache64/128 KiB
(32/64 KiB I-cache with parity,
32/64 KiB D-cache) per core

L2 cache128–512 KiB per core

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This generation of chips starting with the A715 drops native 32-bit support.^[4] It forms part of Arm's Total Compute Solutions 2022 (TCS22) along with Arm's Cortex-X3, Cortex-A510, Arm Immortalis-G715 and CoreLink CI-700/NI-700.^[5]

[1]

[2]

[3]

[4]

[5]

μArch	Cortex-A77	Cortex-A78	Cortex-A710	Cortex-A715	Cortex-A720	Cortex-A725
Codename	Deimos	Hercules	Matterhorn	Makalu	Hunter	Chaberton
Peak clock speed	2.6 GHz	~3.0 GHz				-
Architecture	ARMv8.2-A		ARMv9.0-A		ARMv9.2-A
AArch	-	32-bit and 64-bit		64-bit
Max In-flight	160	160	?	192+^[10]	?	-
L0 (Mops entries)	-	1536^[11]		0^[12]		-
L1 (I + D) (KiB)	64 + 64 KiB	32/64 + 32/64 KiB				64 + 64 KiB
L2 Cache (KiB)	256–512 KiB	128–512 KiB				0.25–1 MiB^[13]
L3 Cache (MiB)	0–4 MiB	0–8 MiB	0–16 MiB		0–32 MiB^[14]
Decode width	4-way			5-way
Dispatch	6 Mops/cycle		5 Mops/cycle^[15]		?	-

ARM Cortex-A715

Architecture changes in comparison with ARM Cortex-A710

Usage

Architecture comparison

See also

References

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