ARM Cortex-A720
High-performance CPU core design
From Wikipedia, the free encyclopedia
The ARM Cortex-A720 is a CPU core model from Arm[1][2] unveiled in 2023.[3] It serves as a successor to the ARM Cortex-A715.[4]
| General information | |
|---|---|
| Launched | 2023 |
| Designed by | ARM Ltd. |
| Cache | |
| L1 cache | 64/128 KiB (32/64 KiB I-cache with parity, 32/64 KiB D-cache) per core |
| L2 cache | 128–512 KiB per core |
| L3 cache | 512 KiB – 32 MiB (optional) |
| Architecture and classification | |
| Microarchitecture | ARM Cortex-A720 |
| Instruction set | ARMv9.2-A |
| Products, models, variants | |
| Product code name |
|
| Variant | |
| History | |
| Predecessor | ARM Cortex-A715 |
| Successor | ARM Cortex-A725 |
Cortex-A700 CPU cores series focus on balanced performance and efficiency, and the CPU core can be paired with other cores in its family such as the high performance ARM Cortex-X4 or/and high efficiency ARM Cortex-A520[5] in a CPU cluster. It can be used as either "big" or "LITTLE".[6]
Architecture changes in comparison with ARM Cortex-A715
- Update to ARMv9.2
- 15% peak performance improvement over the Cortex-A715
- Can down to same size as Cortex-A78 with 10% performance improvement
- Area optimize configuration for no area cost vs Cortex-A78
- Down L2 cache hit latency to 9 cycles (from 10 cycles)
- Down mispredict latency to 11 cycles (from 12 cycles)[6]
- x2 L2 bandwidth
- DSU-120
- Up to 14 cores (up from 12 cores)
- Up to 32 MiB of shared L3 cache (increased from 16 MiB)
Architecture comparison
- "big" core
| μArch | Cortex-A77 | Cortex-A78 | Cortex-A710 | Cortex-A715 | Cortex-A720 | Cortex-A725 |
|---|---|---|---|---|---|---|
| Codename | Deimos | Hercules | Matterhorn | Makalu | Hunter | Chaberton |
| Peak clock speed | 2.6 GHz | ~3.0 GHz | - | |||
| Architecture | ARMv8.2-A | ARMv9.0-A | ARMv9.2-A | |||
| AArch | - | 32-bit and 64-bit | 64-bit | |||
| Max In-flight | 160 | 160 | ? | 192+[7] | - | - |
| L0 (Mops entries) | - | 1536[8] | 0[9] | - | ||
| L1 (I + D) (KiB) | 64 + 64 KiB | 32/64 + 32/64 KiB | 64 + 64 KiB | |||
| L2 Cache (KiB) | 256–512 KiB | 128–512 KiB | 0.25–1 MiB[10] | |||
| L3 Cache (MiB) | 0–4 MiB | 0–8 MiB | 0–16 MiB | 0–32 MiB[11] | ||
| Decode width | 4-way | 5-way | ||||
| Dispatch | 6 Mops/cycle | 5 Mops/cycle[12] | ? | - | ||
Usage
See also
- ARM Cortex-X4, related high performance microarchitecture
- ARM Cortex-A520, related high efficient microarchitecture
- Comparison of ARMv8-A cores