ARM Cortex-X2
Microprocessor core model by ARM
From Wikipedia, the free encyclopedia
The ARM Cortex-X2 is a CPU implementing the ARMv9-A 64-bit instruction set designed by ARM Holdings' Austin design centre as part of ARM's Cortex-X Custom (CXC) program.[1]
| General information | |
|---|---|
| Launched | 2021 |
| Designed by | Arm |
| Performance | |
| Max. CPU clock rate | 2.85 GHz to 3.0 GHz |
| Address width | 40-bit |
| Physical specifications | |
| Cores |
|
| Cache | |
| L1 cache | 128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core |
| L2 cache | 256–1024 KiB per core |
| L3 cache | 512 KiB – 16 MiB (optional) |
| Architecture and classification | |
| Microarchitecture | ARM Cortex-X2 |
| Instruction set | ARMv9.0-A |
| Products, models, variants | |
| Product code name |
|
| Variant | |
| History | |
| Predecessor | ARM Cortex-X1 |
| Successor | ARM Cortex-X3 |
It forms part of Arm's Total Compute Solutions 2021 (TCS21) along with Arm's Cortex-A710, Cortex-A510, Mali-G710 and CoreLink CI-700/NI-700.[2]
Architecture changes in comparison with ARM Cortex-X1
The processor implements the following changes:[3]
- ARMv9.0[4]
- 10 cycle pipeline down from 11, created by reducing the dispatch stage from 2 cycles to 1
- Reorder buffer (ROB) increased by 30% from 224 entries to 288
- dTLB increased by 20% from 40 entries to 48
- SVE2 SIMD support
- Bfloat16 data type support
- Support for Aarch32 removed
- DSU-110
- Up to 12 cores (up from 8 cores)
- Up to 16M L3 cache (up from 8 MB)
- CoreLink CI-700/NI-700
- Up to 32MB SLC
Performance claims:
- Comparing the Cortex-X2[5] to the Cortex-X1 with the same process,
clock speed, and 4MB of L3 cache (also known as ISO-process):- 16% greater integer performance / IPC
- 100% greater ML performance
- 30% peak performance improvement over the Cortex-X1 in smartphones
- (3.3 GHz, 1MB L2, 8MB L3)
- 40% faster than an Intel Core i5-1135G7 at 15W (3.5 GHz, 1MB L2, 16MB L3)
Architecture comparison
- "Prime" core
| uArch | Cortex-A78 | Cortex-X1 | Cortex-X2 | Cortex-X3 | Cortex-X4 | Cortex-X925 |
|---|---|---|---|---|---|---|
| Code name | Hercules | Hera | Matterhorn-ELP | Makalu-ELP | Hunter-ELP | Blackhawk |
| Architecture | ARMv8.2 | ARMv9 | ARMv9.2 | |||
| Peak clock speed | ~3.0 GHz | ~3.3 GHz | ~3.4 GHz | ~3.8 GHz | ||
| Decode width | 4 | 5 | 6 | 10[6] | ||
| Dispatch | 6/cycle | 8/cycle | 10/cycle | |||
| Max in-flight | 2x 160 | 2x 224 | 2x 288 | 2x 320 | 2x 384 | 2x 768 |
| L0 (Mops entries) | 1536[7] | 3072[7] | 1536 | 0[6] | ||
| L1-I + L1-D | 32+32 KiB | 64+64 KiB | ||||
| L2 | 128–512 KiB | 0.25–1 MiB | 0.5–2 MiB | 2–3 MiB | ||
| L3 | 0–8 MiB[8] | 0–16 MiB | 0–32 MiB | |||
Usage
See also
- ARM Cortex-A710, related high performance microarchitecture
- Comparison of ARMv8-A cores, ARMv8 family