ARM Cortex-X4
High-performance CPU core design
From Wikipedia, the free encyclopedia
The ARM Cortex-X4 is a high-performance CPU core from Arm, released in 2023[1] as part of Arm's "total compute solution".[2] It serves as the successor of ARM Cortex-X3.[3]
| General information | |
|---|---|
| Launched | 2023 |
| Designed by | ARM Ltd. |
| Performance | |
| Address width | 40-bit |
| Physical specifications | |
| Cores |
|
| Cache | |
| L1 cache | 128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core |
| L2 cache | 512–2048 KiB per core |
| L3 cache | 512 KiB – 32 MiB (optional) |
| Architecture and classification | |
| Microarchitecture | ARM Cortex-X4 |
| Instruction set | ARMv9.2-A |
| Products, models, variants | |
| Product code name |
|
| Variant | |
| History | |
| Predecessor | ARM Cortex-X3 |
| Successor | ARM Cortex-X925 |
X-series CPU cores generally focus on high performance, and can be grouped with other ARM cores, such as ARM Cortex-A720 or/and ARM Cortex-A520 in a System-on-Chip (SoC).[4][5]
Architecture changes in comparison with ARM Cortex-X3
The processor implements the following changes:[3][4][5]
- ARMv9.2
- micro-op (MOP) cache removed (previously 1.5k entries)
- Decode width: 10
- Rename / Dispatch width: 10 (increased from 8)
- Reorder buffer (ROB): 384 entries (increased from 320)
- Execution ports: 21 (increased from 15)
- Pipeline length: 10 (increased from 9)
- Up to 2 MiB of private L2 cache (increased from 1 MiB)
- DSU-120
- Up to 14 cores (up from 12 cores)
- Up to 32 MiB of shared L3 cache (increased from 16 MiB)
Performance claims:
- 15% peak performance improvement over the Cortex-X3 in smartphones
- (3.4GHz, 2MB L2, 8MB L3).[5]
- 13% IPC uplift over the Cortex-X3, when based on the same process, clock speed,
- and L3 cache (but 2 MiB L2 vs 1 MiB L2) setup (also known as ISO-process).[5]
Architecture comparison
- "Prime" core
| uArch | Cortex-A78 | Cortex-X1 | Cortex-X2 | Cortex-X3 | Cortex-X4 | Cortex-X925 |
|---|---|---|---|---|---|---|
| Code name | Hercules | Hera | Matterhorn-ELP | Makalu-ELP | Hunter-ELP | Blackhawk |
| Architecture | ARMv8.2 | ARMv9 | ARMv9.2 | |||
| Peak clock speed | ~3.0 GHz | ~3.3 GHz | ~3.4 GHz | ~3.8 GHz | ||
| Decode width | 4 | 5 | 6 | 10[6] | ||
| Dispatch | 6/cycle | 8/cycle | 10/cycle | |||
| Max in-flight | 2x 160 | 2x 224 | 2x 288 | 2x 320 | 2x 384 | 2x 768 |
| L0 (Mops entries) | 1536[7] | 3072[7] | 1536 | 0[6] | ||
| L1-I + L1-D | 32+32 KiB | 64+64 KiB | ||||
| L2 | 128–512 KiB | 0.25–1 MiB | 0.5–2 MiB | 2–3 MiB | ||
| L3 | 0–8 MiB[8] | 0–16 MiB | 0–32 MiB | |||
Usage
See also
- ARM Cortex-A520, related high efficient microarchitecture
- ARM Cortex-A720, related efficient sustained performance microarchitecture
- Comparison of ARMv8-A cores