ARM Cortex-A710

ARM Cortex-A710
General information
Launched	2021
Designed by	ARM Ltd.
Cache
L1 cache	64/128 KiB ; (32/64 KiB I-cache with parity, ; 32/64 KiB D-cache) per core
L2 cache	256/512 KiB per core
L3 cache	256 KiB – 16 MiB (optional)
Architecture and classification
Microarchitecture	ARM Cortex-A710
Instruction set	ARMv9.0-A
Products, models, variants
Product code name	Matterhorn;
Variant	ARM Cortex-X2;
History
Predecessor	ARM Cortex-A78
Successor	ARM Cortex-A715

The ARM Cortex-A710 is the successor to the ARM Cortex-A78, being the First-Generation Armv9 "big" Cortex CPU.^[1] It is the companion to the ARM Cortex-A510 "LITTLE" efficiency core. It was designed by ARM Ltd.'s Austin centre.^[2] It is the fourth and last iteration of Arm's Austin core family.^[2]

Launched2021

Designed byARM Ltd.

L1 cache64/128 KiB
(32/64 KiB I-cache with parity,
32/64 KiB D-cache) per core

L2 cache256/512 KiB per core

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It forms part of Arm's Total Compute Solutions 2021 (TCS21) along with Arm's Cortex-X2, Cortex-A510, Mali-G710 and CoreLink CI-700/NI-700.^[3]

[1]

[2]

[3]

μArch	Cortex-A77	Cortex-A78	Cortex-A710	Cortex-A715	Cortex-A720	Cortex-A725
Codename	Deimos	Hercules	Matterhorn	Makalu	Hunter	Chaberton
Peak clock speed	2.6 GHz	~3.0 GHz				-
Architecture	ARMv8.2-A		ARMv9.0-A		ARMv9.2-A
AArch	-	32-bit and 64-bit		64-bit
Max In-flight	160	160	?	192+^[5]	?	-
L0 (Mops entries)	-	1536^[6]		0^[7]		-
L1 (I + D) (KiB)	64 + 64 KiB	32/64 + 32/64 KiB				64 + 64 KiB
L2 Cache (KiB)	256–512 KiB	128–512 KiB				0.25–1 MiB^[8]
L3 Cache (MiB)	0–4 MiB	0–8 MiB	0–16 MiB		0–32 MiB^[9]
Decode width	4-way			5-way
Dispatch	6 Mops/cycle		5 Mops/cycle^[10]		?	-

ARM Cortex-A710

Architecture changes in comparison with ARM Cortex-A78

Architecture comparison

Usage

See also

References

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