Elbrus 2000
Microprocessor designed by the Moscow Center of SPARC Technologies
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The Elbrus 2000 (or e2k; Russian: Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.
| General information | |
|---|---|
| Launched | 2007 |
| Designed by | Moscow Center of SPARC Technologies (MCST) |
| Common manufacturer | |
| Performance | |
| Max. CPU clock rate | 300 MHz |
| Physical specifications | |
| Cores |
|
| Architecture and classification | |
| Instruction set | Elbrus |
It supports two instruction set architectures (ISA): Elbrus VLIW and Intel x86 (a complete, system-level implementation with a software dynamic binary translation virtual machine, similar to Transmeta Crusoe).
Due to its unique architecture, the Elbrus 2000 can execute 20 instructions per clock, so even with its modest clock speed it can compete with much faster clocked superscalar microprocessors when running in native VLIW mode.[1][2] For security reasons, the Elbrus 2000 architecture implements dynamic data type-checking during execution. In order to prevent unauthorized access, each pointer has additional type information that is verified when the associated data is accessed.[3]
Supported operating systems
Elbrus 2000 information
| Produced | 2005 |
| Process | CMOS 0.13 μm |
| Clock rate | 300 MHz |
| Peak performance |
|
| Data format |
|
| Cache |
|
| Data transfer rate |
|
| Transistors | 75.8 million |
| Connection layers | 8 |
| Packing / pins | HFCBGA / 900 |
| Chip size | 31×31×2.5 mm |
| Voltage | 1.05 / 3.3 V |
| Power consumption | 6 W |
Comparative
| Russian Designation | English Designation | e2k architecture | Cores | GHz | GFLOPS | NUMA | L2 (MB) | L3 (MB) | RAM | Graphics card | Int. Southbridge | Ext. Southbridge | Watts | Technical process(nm) | Year |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Эльбрус | Elbrus | v1 | 1 | 0.300 | 2.4 | No | ¼ | No | ext. counter | No | No | No | 6 | 130 | 2007 |
| Эльбрус-S | Elbrus-S | v2 | 1 | 0.500 | 4 | 4 | 2 | No | 3×DDR3-1600 | No | No | KPI-1 | 13 | 90 | 2010 |
| Эльбрус-2C+ | Elbrus-2C+ | v2 | 2 | 0.500 | 8 | 4 | 2 | No | 3×DDR3-1600 | No | No | KPI-1 | 25 | 90 | 2012 |
| Эльбрус-4С | Elbrus-4C | v3 | 4 | 0.800 | 25 | 4 | 8 | No | 3×DDR3-1600 | No | No | KPI-1 | 45 | 65 | 2013 |
| Эльбрус-1С+ | Elbrus-1C+ | v4 | 1 | 1.000 | 12 | No | 2 | No | 2×DDR3-1600 | MGA2 + GC2500 | No | KPI-2 | 10 | 40 | 2016 |
| Эльбрус-8С | Elbrus-8S | v4 | 8 | 1.300 | 125 | 4 | 4 | 16 | 4×DDR3-1600 | No | No | KPI-2 | 80 | 28 | 2016 |
| Эльбрус-1СК | Elbrus-1SK | v4 | 1 | 1.000 | 12 | No | 2 | No | 1×DDR3-1600 | MGA2 + GC2500 | KPI-2 | No | 20 | 40 | 2018 |
| Эльбрус-8С1 | Elbrus-8S1 | v4 | 8 | 1.300 | 125 | 4 | 4 | 16 | 4×DDR3-1600 | No | No | KPI-2 | 80 | 28 | 2018 |
| Эльбрус-8СВ | Elbrus-8SV | v5 | 8 | 1.500 | 288 | 4 | 4 | 16 | 4×DDR4-2400 | No | No | KPI-2 | 90 | 28 | 2018 |
| Эльбрус-2С3 | Elbrus-2S3 | v6 | 2 | 2.000 | 96 | No | 4 | No | 2×DDR4-2400 | MGA2.5 + GX6650 | EIOH | KPI-2 | 10 | 16 | 2021 |
| Эльбрус-12C | Elbrus-12S | v6 | 12 | 2.000 | 576 | 2 | 12 | 24 | 2×DDR4-2666 | No | EIOH | KPI-2 | 100 | 16 | 2021 |
| Эльбрус-16C | Elbrus-16S | v6 | 16 | 2.000 | 768 | 4 | 16 | 32 | 8×DDR4-2666 | No | EIOH | KPI-2 | 120 | 16 | 2021 |
| Эльбрус-32C | Elbrus-32S | v7 | 32 | 2.500 | 1500 | 4 | ? | ? | 6×DDR5 | No | ? | ? | ? | 7 | 2025 |
| Legend: Old model Current model Future model | |||||||||||||||
Note: in the "Year" column the date of completion of the development work on the creation of the "microcircuit" is indicated. The appearance on the market of ready-made computing modules and machines takes at least 1 year, and multiprocessor systems and complex computing systems – at least 2 years.