GDDR SDRAM
Type of memory used on graphics cards
From Wikipedia, the free encyclopedia
Graphics DDR SDRAM (GDDR SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) specifically designed for applications requiring high bandwidth,[1] e.g. graphics processing units (GPUs). GDDR SDRAM is distinct from the more widely known types of DDR SDRAM, such as DDR4 and DDR5, although they share some of the same features—including double data rate (DDR) data transfers. As of 2025[update], GDDR SDRAM has been succeeded by GDDR2, GDDR3, GDDR4, GDDR5, GDDR5X, GDDR6, GDDR6X, GDDR6W and GDDR7.
Generations
- Hynix GDDR SDRAM
- A Samsung GDDR3 256MBit package
- A 512 MBit Qimonda GDDR3 SDRAM package
- Inside a Samsung GDDR3 256MBit package
DDR SGRAM
GDDR was initially known as DDR SGRAM (double data rate synchronous graphics RAM). It was commercially introduced as a 16 Mb memory chip by Samsung Electronics in 1998.[2] Compared to DDR SDRAM which is byte-accessible, GDDR SDRAM is block-accessible.[3]
GDDR2
GDDR3
GDDR4
GDDR5
GDDR6
GDDR7
Table of transfer rates
| Module type | Chip type | Memory clock | Transfers/s | Transfers/clock | Transfer rate | |
|---|---|---|---|---|---|---|
| 32 lanes | GDDR2 | 400–500 MHz | 0.8–1.0 GT/s | 2 | 25.6–32.0 Gbit/s | 3.2–4.0 GB/s |
| 32 lanes | GDDR3 | 400–1000 MHz | 0.8–2.0 GT/s | 2 | 25.6–64.0 Gbit/s | 3.2–8.0 GB/s |
| 32 lanes | GDDR4 | 868–1126 MHz | 1.7–2.3 GT/s | 2 | 55.6–72.1 Gbit/s | 6.9–9.0 GB/s |
| 32 lanes | GDDR5[4] | 1000–2000 MHz | 4.0–8.0 GT/s | 4 | 128.0–256.0 Gbit/s | 16.0–32.0 GB/s |
| 32 lanes | GDDR5X[5] | 1000–1808 MHz | 8.0–14.5 GT/s | 8 | 256.0–462.8 Gbit/s | 32.0–57.9 GB/s |
| 32 lanes | GDDR6 | 1375–2500 MHz | 11.0–20.0 GT/s | 8 | 352.0–640.0 Gbit/s | 44.0–80.0 GB/s |
| 32 lanes | GDDR6X | 1188–1438 MHz | 19.0–23.0 GT/s | 16 | 608.0–736.0 Gbit/s | 76.0–92.0 GB/s |
| 64 lanes | GDDR6W | 1375 MHz | 22.0 GT/s | 16 | 1408.0 Gbit/s | 176.0 GB/s |
| 32 lanes | GDDR7 | 1750–2500 MHz | 28.0–40.0 GT/s | 16 | 896.0–1280.0 Gbit/s | 112.0–160.0 GB/s |
(1 lane is equivalent to 1 bit/transfer.)