IBM Telum
2021 64-bit mainframe microprocessor by IBM
From Wikipedia, the free encyclopedia
Telum is a microprocessor made by IBM for the IBM z16 series mainframe computers.[2][3] The processor was announced at the Hot Chips 2021 conference on 23 August 2021.[2] Telum is IBM's first processor that contains on-chip acceleration for artificial intelligence inferencing while a transaction is taking place.[clarification needed][4][5]
| General information | |
|---|---|
| Launched | 2021 |
| Designed by | IBM |
| Common manufacturer | |
| Performance | |
| Max. CPU clock rate | 5.2 GHz |
| Physical specifications | |
| Cores |
|
| Cache | |
| L2 cache | 32 MB per core |
| Architecture and classification | |
| Technology node | 7 nm |
| Instruction set | z/Architecture |
| History | |
| Predecessor | z15 |
| Successor | Telum II |
Description
The chip contains 8 processor cores with a deep superscalar out-of-order pipeline, running with more than 5 GHz clock frequency which is optimized for the demands of heterogenous enterprise-class workloads (e.g: finance, security sensitive applications, applications requiring extreme reliability). The cache and chip-interconnection infrastructure provides 32 MB cache per core and can scale to 32 Telum chips.[6][3][7] The cache design has been described as "revolutionary" in 2021,[6] by creating a system where the L2 cache of one core can be used as virtual L3 and L4 caches for another core.[3][1] The Telum processor can either be water cooled or air cooled, but water cooling is required for running more than a few Telum processors in a single IBM compute drawer.[8][9] Unlike other processors, the IBM Telum does not thermal throttle by reducing clock speed; instead it inserts sleep state instructions.[8][9]
Telum adds a new 16-bit floating point format (NNP-Data-Type-1 Format) and several new instructions.[10] The Neural Network Processing Assists (NNPA)[11] instruction performs a variety of tensor instructions useful for neural networks.[a]
Telum II adds new functions to NNPA.[12]
See also
Manuals
- z-14
- z/Architecture Principles of Operation (PDF) (Fourteenth ed.). IBM. May 2022. pp. 26-61 – 26-96. SA22-7832-13. Retrieved March 31, 2025.
- z-15
- z/Architecture Principles of Operation (PDF) (Fifteenth ed.). IBM. April 2025. SA22-7832-14. Retrieved March 31, 2025.
Notes
- The NNPA instruction does not specify its operands; rather, General Register 0 contains a function code (FC) and General Register 1 contains the address of a parameter block. Depending on the function, the parameter block may contain up to 4 tensor descriptors.