Analog-to-digital converter

Resolution

The resolution of the converter indicates the number of different, i.e., discrete, values it can produce over the allowed range of analog input values. Thus, a particular resolution determines the magnitude of the quantization error and therefore determines the maximum possible signal-to-noise ratio for an ideal ADC without the use of oversampling. The input samples are usually stored electronically in binary form within the ADC, so the resolution is usually expressed in bits.

Resolution can also be defined electrically, and expressed in volts. The change in voltage required to guarantee a change in the output code level is called the least significant bit (LSB) voltage. The resolution Q of the ADC is equal to the LSB voltage. The voltage resolution of an ADC is equal to its overall voltage measurement range divided by the number of intervals:

${\displaystyle Q={\dfrac {E_{\mathrm {FSR} }}{2^{M}}},}$

where M is the ADC's resolution in bits and E_FSR is the full-scale voltage range (also called 'span'). E_FSR is given by

${\displaystyle E_{\mathrm {FSR} }=V_{\mathrm {RefHi} }-V_{\mathrm {RefLow} },\,}$

where V_RefHi and V_RefLow are the upper and lower extremes, respectively, of the voltages that can be coded.

Normally, the number of voltage intervals is given by

${\displaystyle N=2^{M},\,}$

where M is the ADC's resolution in bits.^[1]

That is, one voltage interval is assigned in between two consecutive code levels.

Example:

• Coding scheme as in figure 1
• Full scale measurement range = 0 to 1 volt
• ADC resolution is 3 bits: 2³ = 8 quantization levels (codes)
• ADC voltage resolution, Q = 1 V / 8 = 0.125 V.

In many cases, the useful resolution of a converter is limited by the signal-to-noise ratio (SNR) and other errors in the overall system expressed as an ENOB.

Quantization error

Quantization error is introduced by the quantization inherent in an ideal ADC. It is a rounding error between the analog input voltage to the ADC and the output digitized value. The error is nonlinear and signal-dependent. In an ideal ADC, where the quantization error is uniformly distributed between −1⁄2 LSB and +1⁄2 LSB, and the signal has a uniform distribution covering all quantization levels, the signal-to-quantization-noise ratio (SQNR) is given by

${\displaystyle \mathrm {SQNR} =20\log _{10}({\dfrac {E_{\mathrm {FSR} }}{\tfrac {E_{\mathrm {FSR} }}{2^{M}}}})=20\log _{10}(2^{M})\approx 6.02\cdot M\ \mathrm {dB} \,\!}$^[2]

where ${\displaystyle M}$ is the number of quantization bits. For example, for a 16-bit ADC, the quantization error is 96.3 dB below the maximum level.

Quantization error is distributed from DC to the Nyquist frequency. Consequently, if part of the ADC's bandwidth is not used, as is the case with oversampling, some of the quantization error will occur out-of-band, effectively improving the SQNR for the bandwidth in use. In an oversampled system, noise shaping can be used to further increase SQNR by forcing more quantization error out of band.

Accuracy

An ADC has several sources of errors. Quantization error and (assuming the ADC is intended to be linear) non-linearity are intrinsic to any analog-to-digital conversion. These errors are measured in a unit called the least significant bit (LSB). In the above example of an 8-bit ADC, an error of one LSB is 1⁄256 of the full signal range, or about 0.4%.

Jitter

When digitizing a sine wave ${\displaystyle x(t)=A\sin {(2\pi f_{0}t)}}$, the use of a non-ideal sampling clock will result in some uncertainty in when samples are recorded. Provided that the actual sampling time uncertainty due to clock jitter is ${\displaystyle \Delta t}$, the error caused by this phenomenon can be estimated as ${\displaystyle E_{ap}\leq |x'(t)\Delta t|\leq 2A\pi f_{0}\Delta t}$. This will result in additional recorded noise that will reduce the effective number of bits (ENOB) below that predicted by quantization error alone. The error is zero for DC, small at low frequencies, but significant with signals of high amplitude and high frequency. The effect of jitter on performance can be compared to quantization error: ${\displaystyle \Delta t<{\frac {1}{2^{q}\pi f_{0}}}}$, where q is the number of ADC bits.^{[citation needed]}

Clock jitter is caused by phase noise.^[3][4] The resolution of ADCs with a digitization bandwidth between 1 MHz and 1 GHz is limited by jitter.^[5] For lower bandwidth conversions such as when sampling audio signals at 44.1 kHz, clock jitter has a less significant impact on performance.^[6]

Sampling rate

An analog signal is continuous in time and it is necessary to convert this to a flow of digital values. It is therefore required to define the rate at which new digital values are sampled from the analog signal. The rate of new values is called the sampling rate or sampling frequency of the converter. A continuously varying bandlimited signal can be sampled and then the original signal can be reproduced from the discrete-time values by a reconstruction filter. The Nyquist–Shannon sampling theorem implies that a faithful reproduction of the original signal is only possible if the sampling rate is higher than twice the highest frequency of the signal.

Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held constant during the time that the converter performs a conversion (called the conversion time). An input circuit called a sample and hold performs this task—in most cases by using a capacitor to store the analog voltage at the input, and using an electronic switch or gate to disconnect the capacitor from the input. Many ADC integrated circuits include the sample and hold subsystem internally.

Flash

A flash ADC, also known as a parallel search ADC,^[8] employs a bank of voltage comparators sampling the input signal in parallel, each with a different voltage threshold. The circuit consists of a resistive divider network, an array of voltage comparators and a priority encoder. Each node of the resistive divider provides a voltage threshold for one comparator. The comparator outputs are applied to a priority encoder, which generates a binary number proportional to the input voltage.

Flash ADCs have a large die size and high power dissipation. They are used in a variety of applications, including video, wideband communications, and for digitizing other fast signals.

The circuit performs high speed conversions as the voltage comparators operate concurrently, in parallel. Typical conversion time is 100 ns or less. For each additional output bit, the number of comparators almost doubles, the priority encoder becomes more complex, and power doubles, but conversion time does not significantly increase.^[9]

Successive approximation

A successive-approximation ADC uses a voltage comparator, digital-to-analog converter (DAC), and sequential logic to digitize via a binary search, producing one bit of the ADC output word per clock cycle. The sequential logic, known as the successive-approximation register (SAR), is a finite-state machine that embodies the binary search algorithm. The binary word issued by the SAR serves as both ADC output and DAC control input.

The DAC output voltage range defines the allowed input voltage range. In the first clock cycle, the most significant SAR bit (MSB) is set, thus programming the DAC to the midpoint of the voltage range as a first approximation. At each successive clock cycle, the input and DAC voltages are compared, the SAR bit is cleared or left set depending on the result of this comparison (thus resolving the output bit and narrowing the voltage range for the next comparison), and the next (less significant) SAR bit is set for the next approximation. At each step in this process, the approximation value stored in the SAR resolves one ADC output bit and narrows the remaining voltage search range by half. The conversion is completed when the SAR least significant bit (LSB) has been resolved.

Ramp-compare

A ramp-compare ADC uses a sawtooth wave generator, voltage comparator, and digital counter to perform analog-to-digital conversions. It produces a sawtooth signal whose voltage linearly ramps up or down from zero volts,^[10] which is applied to one input of the comparator. The analog input voltage is applied to the other comparator input.

Various techniques are used to generate the sawtooth wave. For example, nonlinear ramps can be produced by a microcontroller in conjunction with a resistor and capacitor.^[11] When using an analog integrator to generate the ramp, the ramp duration may be sensitive to temperature. To avoid this, a DAC may be used to generate the ramp, with DAC inputs driven by the counter as shown in the example circuit below.

Upon start of conversion, a voltage ramp begins, the count is zeroed and the counter starts counting constant-frequency clock pulses. When the ramp reaches the input voltage, the comparator output changes state. This state change causes the accumulated count to be copied to a holding register, which serves as the ADC output. The ADC output value is proportional to the input voltage. The holding register retains and issues the ADC data while the next conversion is in progress.

Dual-slope integrating

An integrating ADC (also dual-slope or multi-slope ADC) uses an integrator, voltage comparator, counter and control logic to perform analog-to-digital conversions. The buffered input voltage is applied to the integrator and the integrator output voltage is allowed to ramp up for a fixed time (the run-up period). A reference voltage of opposite polarity is then applied to the integrator and the integrator output is allowed to ramp down until it returns to zero (the run-down period). The periods are measured in units of the converter's clock period.

The input voltage is computed as a function of the reference voltage, run-up period, and run-down period. Longer integration times provide higher resolution, but the conversion time doubles for each additional bit of resolution,^[9] and consequently this type of ADC is well suited for measuring slowly varying signals such as thermocouples and weighing scales. Converters of this type (or related variations) are commonly used in digital voltmeters.

Tracking

A tracking ADC employs a negative feedback loop consisting of a voltage comparator, an up/down counter clocked at a fixed rate, and a digital-to-analog converter (DAC), to track (continuously follow and match) the analog input voltage.^[12] The comparator produces a digital signal indicating whether the DAC voltage is less than or greater than the input voltage, which in turn causes the count to increment or decrement, respectively, every clock cycle. The counter outputs are used as DAC input data, and consequently the DAC voltage—and by virtue of tracking, the analog input voltage—is indicated by the count.

When starting conversions, the initial conversion time is proportional to the analog input voltage. Tracking converters are suitable for measuring low-frequency signals that have a maximum slew rate less than that of the DAC voltage at the maximum tracking slew rate.

Pipelined

A pipelined ADC (also called subranging quantizer) uses two or more conversion steps. First, a coarse conversion is done. In a second step, the difference to the input signal is determined with a DAC. This difference is then converted more precisely, and the results are combined in the last step. This can be considered a refinement of the successive-approximation ADC wherein the feedback reference signal consists of the interim conversion of a whole range of bits (for example, four bits) rather than just the next-most-significant bit. By combining the merits of the successive approximation and flash ADCs this type is fast, has a high resolution, and can be implemented efficiently.

Delta–sigma

A delta–sigma ADC (also known as a sigma–delta ADC) consists of a delta–sigma modulator followed by a digital filter. The analog input voltage is applied to the modulator, which responds by producing a bit stream in which the ratio of logic ones to zeros is proportional to the input voltage.^[13] The resulting bit stream, whose bit rate is much higher than the ADC data output rate, is then processed by a downsampling digital filter to produce ADC output data at a lower word rate.

• 
  Example first-order, delta–sigma analog-to-digital converter (ADC), based on a first-order delta–sigma modulator and second-order CIC filter

The modulator is based on a negative feedback loop consisting of one or more analog integrators, a voltage comparator, and a one-bit digital-to-analog converter (DAC). The feedback loop continuously corrects accumulated quantization errors and performs noise shaping, thus causing quantization noise to be reduced in the low frequencies of interest and increased in higher frequencies. The digital filter removes the higher frequencies -- and associated noise -- and converts the data stream from the high modulator sampling rate with its low bit depth to a lower rate with higher bit depth.

Voltage-to-frequency

A voltage-to-frequency (V/F) ADC, also known as an intermediate frequency modulator (FM) ADC, employs a voltage-to-frequency converter (VFC) in conjunction with a frequency counter to perform analog-to-digital conversions. The analog input voltage serves as a control input to the VFC, which in turn outputs a periodic signal with frequency proportional to the input voltage. The frequency counter measures the VFC output frequency, issuing the measurement as a binary value (the ADC output) which is proportional to the frequency, and thus also proportional to the analog input voltage.

Each measurement made by the frequency counter occurs over the course of an interval known as the gate time. Since the analog input voltage, and consequently the VFC frequency, can change during the gate time, the measurement is effectively an integrating conversion, with integration time equal to the gate time. Longer gate times result in slower conversions and higher measurement resolution, whereas shorter gate times result in faster conversions and lower resolution.

The VFC and frequency counter communicate via a single digital signal. Consequently, they can easily be distantly separated, and the VFC output signal may be conveyed through an opto-isolator or wirelessly, thus facilitating galvanic isolation between the analog input and ADC output circuits. Such ADCs are widely used for this purpose, and were once the most popular way to digitize remote analog sensors.^{[14][15][16][17][18]}

Wilkinson

A Wilkinson ADC performs analog-to-digital conversions by storing the voltage to be measured on a capacitor, and then discharging the capacitor at a constant rate while measuring the discharge time with a binary counter.^[19] When the ADC is idling (not digitizing), the analog input voltage is electrically connected to the capacitor, thus causing the capacitor voltage to track the input voltage, and counting is disabled. Upon start of conversion, the capacitor is disconnected from the analog input — leaving the voltage to be converted stored on the capacitor — and the counter is zeroed. The capacitor is then connected to a constant current source and the counter is enabled. The current source discharges the capacitor at a constant rate, resulting in a negative-sloped, linear voltage ramp whose duration is proportional to the sample voltage. While the voltage is ramping down, the counter counts constant-frequency clock pulses.^[19] When the ramp reaches zero volts, the conversion has finished and the converter returns to idle mode. The binary number output by the halted counter is a measure of the ramp time, and thus is proportional to the measured voltage.^[19]

The Wilkinson ADC was designed by Denys Wilkinson in 1950.^[20][21] The conversion time is inversely proportional to the clock frequency and proportional to the input amplitude. Due to the latter, higher voltages result in longer conversion times.

Wilkinson converters were widely used in multichannel analyzers for nuclear spectroscopy through the 1960s and 1970s.^[22][23] In such applications, a peak detector is typically used to detect voltage pulses at the analog input. The peak detector starts an ADC conversion upon detecting the peak of an input pulse, thus leaving the peak voltage stored on the capacitor, and consequently the resulting ADC data is a measure of the peak input voltage.

Time-stretch

A time-stretch analog-to-digital converter (TS-ADC) digitizes a high-bandwidth analog signal by time-stretching the signal prior to digitization. It commonly uses a photonic preprocessor to time-stretch the signal, which effectively slows the signal down in time and compresses its bandwidth. As a result, an ADC which is too slow to capture the original signal can capture the stretched signal.

To allow continuous capture of the signal, the front end divides the stretched signal into multiple segments so that each segment may be digitized by a separate ADC. A digital signal processor rearranges the acquired samples and removes any distortions added by the preprocessor to yield a unified binary data stream that accurately represents the original analog signal.

Interleaved ADCs

Two or more ADCs may be interleaved to achieve a sampling rate higher than that of the individual ADCs and reduce the signal-to-noise ratio.^[24] In a time-interleaved ADC consisting of M ADCs, the sampling clock is phase-shifted by a different amount for each ADC so that their sampling times are uniformly distributed over a clock period, thus increasing their combined sample rate to M times the sample rate of each individual ADC. In practice, individual ADC differences degrade the overall performance of such circuits, reducing the spurious-free dynamic range (SFDR).^[25] However, techniques exist to correct for these mismatch errors.^[26]

Sliding scale method

In 1963, the sliding scale method was introduced as a way to reduce differential nonlinearity in ADCs used in radiation detection systems.^[27] In such applications, the ADC samples are accumulated into histogram "bins" representing measured particle energies. If some samples correspond to slightly wider or narrower input voltage ranges than others, the resulting bins are uneven, resulting in visible structure in what should be smooth spectra.

The method works by adding a known, random analog offset to the input before conversion and subtracting the corresponding digital value from the resulting ADC sample. Although the final numerical result is unchanged, each conversion effectively occurs at a different position along the ADC transfer characteristic. When many samples are accumulated, the output codes represent an average over several adjacent code widths, reducing the impact of differential nonlinearity.^[28][29]

Measuring physical values other than voltage

Analog-to-digital converters are often used to acquire data from physical processes that do not directly produce voltages. Example of this include:

• Capacitive sensing converts from the analog physical quantity of a capacitance. That capacitance could be a proxy for some other physical quantity, such as the distance some metal object is from a metal sensing plate, or the amount of water in a tank, or the permittivity of a dielectric material.
• Sensors in general that don't directly produce a voltage may indirectly produce a voltage or, through other ways, be converted into a digital value.
  • Resistive output (e.g., from a potentiometer or a force-sensing resistor) can be made into a voltage by sending a known current through it, or can be made into an RC charging time measurement, to produce a digital result.

Music recording

Analog-to-digital converters are widely used to convert analog music signals to digital data streams, and are integral to modern music reproduction technology and digital audio workstation-based sound recording. In many cases they are used to create pulse-code modulation (PCM) data streams that are stored as digital music files on compact discs and other storage media. ADCs utilized in music typically sample at rates up to 192 kilohertz. Many recording studios record in 24-bit 96 kHz pulse-code modulation (PCM) format and then downsample and dither the signal for Compact Disc Digital Audio production (44.1 kHz) or to 48 kHz for radio and television broadcast applications.

Digital signal processing

ADCs are required in digital signal processing systems that process, store, or transport virtually any analog signal in digital form. TV tuner cards, for example, use fast video analog-to-digital converters. Slow on-chip 8-, 10-, 12-, or 16-bit analog-to-digital converters are common in microcontrollers. Digital storage oscilloscopes need very fast analog-to-digital converters, also crucial for software-defined radio and their new applications.

Scientific instruments

Digital imaging systems commonly use analog-to-digital converters for digitizing pixels. Some radar systems use analog-to-digital converters to convert signal strength to digital values for subsequent signal processing. Many other in situ and remote sensing systems commonly use analogous technology.

Many sensors in scientific instruments produce an analog signal; temperature, pressure, pH, light intensity etc. All these signals can be amplified and fed to an ADC to produce a digital representation.

Displays

Flat-panel displays are inherently digital and need an ADC to process an analog signal such as composite or VGA.