Zen 5

Branch prediction

Zen 5's changes to branch prediction are the most significant divergence from any previous Zen microarchitecture. The branch predictor in a core tries to predict the outcome when there are diverging code paths. Zen 5's branch predictor is able to operate two-ahead where it can predict up to two branches per clock cycle. Previous architectures were limited to one branch instruction per clock cycle, limiting the instruction-fetch throughput of branch-heavy programs.^[23] Two-ahead branch predictors have been discussed in academic research dating back to André Seznec et al.'s 1996 paper "Multiple-block ahead branch predictors".^[24] 28 years after it was first proposed in academic research, AMD's Zen 5 architecture became the first microarchitecture to fully implement two-ahead branch prediction.^[4] Increased data prefetching assists the branch predictor.^[4]

Integer units

Zen 5 contains six Arithmetic Logic Units (ALUs), up from four ALUs in prior Zen architectures. A greater number of ALUs that handle common integer operations can increase per-cycle scalar integer throughput by 50%.^[25]

Vector engines and instructions

The vector engine in Zen 5 features four floating-point pipes compared to three pipes in Zen 4. Zen 4 introduced AVX-512 instructions. AVX-512 capabilities have been expanded with Zen 5 with a doubling of the floating-point pipe width to a native 512-bit floating-point datapath. The AVX-512 datapath is configurable depending on the product. Ryzen 9000 series desktop processors and EPYC 9005 server processors feature the full 512-bit datapath, but Ryzen AI 300 mobile processors feature a 256-bit datapath to reduce power consumption. AVX-512 instruction has been extended to VNNI/VEX instructions. Additionally, there is greater bfloat16 throughput.^[4]

L1

The wider front end in the Zen 5 architecture necessitates larger caches and higher memory bandwidth in order to keep the cores fed with data. The L1 cache per core is increased from 64 KB to 80 KB per core. The L1 instruction cache remains the same at 32 KB but the L1 data cache is increased from 32 KB to 48 KB per core. Furthermore, the bandwidth of the L1 data cache for 512-bit floating-point unit pipes has also been doubled. The L1 data cache's associativity has increased from 8-way to 12-way in order to accommodate its larger size.^[4]

L2

The L2 cache remains at 1 MB but its associativity has increased from 8-way to 16-way. Zen 5 also has a doubled L2 cache bandwidth of 64 bytes per clock.^[4]

L3

The L3 cache is filled from L2 cache victims and in-flight misses. Latency for accessing the L3 cache has been reduced by 3.5 cycles.^[26] A Zen 5 Core Complex Die (CCD) contains 32 MB of L3 cache shared between the 8 cores. In Zen 5 3D V-Cache CCDs, a piece of silicon containing 64 MB of extra L3 cache is placed under the cores rather than on top like in prior generations for a total of 96 MB.^[27] This allows for increased core frequency compared to previous generation 3D V-Cache implementations which were sensitive to higher voltages. The Zen 5-based Ryzen 7 9800X3D has a 500 MHz increased base frequency over the Zen 4-based Ryzen 7 7800X3D and allows overclocking for the first time.^[28]

Ryzen AI 300 APUs, codenamed "Strix Point", features 24 MB of total L3 cache which is split into two separate cache arrays. 16 MB of dedicated L3 cache is shared by the 4 Zen 5 cores and 8 MB is shared by the 8 Zen 5c cores.^[29] Zen 5c cores are not able to access the 16 MB L3 cache array and vice versa.^[30]

Granite Ridge

AMD announced an initial lineup of four models of Ryzen 9000 processors on June 3, 2024, including one Ryzen 5, one Ryzen 7 and two Ryzen 9 models. Manufactured on a 4 nm process, the processors feature between 6 and 16 cores.^[33] Ryzen 9000 processors were released in August 2024.^[4]

In May 2025 four of these processors were also released in the 4005 range of the EPYC brand,^[34] with the 4585PX corresponding to the 9950X3D, the 4565P to the 9950X, the 4345P to the 9700X, and the 4245P to the 9600. Two EPYC 4005 parts, both 65W, have no direct Ryzen 9000 series equivalent: the EPYC 4465P with 12 cores at 3.4 GHz, and the 4545P with sixteen cores at 3.0 GHz.^[34]

Common features of Ryzen 9000 desktop CPUs:

• Socket: AM5.
• All the CPUs support DDR5-5600 RAM in dual-channel mode in 2x1R and 2x2R configuration, but only DDR5-3600 for 4x1R and 4x2R.
• All the CPUs support 28 PCIe 5.0 lanes. 4 of the lanes are reserved as link to the chipset.
• Includes integrated RDNA 2 GPU with 2 CUs and base and boost clock speeds of 0.4 GHz and 2.2 GHz, respectively. Models with "F" suffixes are without iGPUs.
• L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
• L2 cache: 1 MB per core.
• Models with an "X3D" suffix include 2nd-generation 3D V-Cache in the form of a 64 MB cache die, which augments the L3 cache of one CCD.^[35]
• Fabrication process: TSMC N4X FinFET (N6 FinFET for the I/O die).

Shimada Peak

AMD announced the Threadripper 9000 series of high-end desktop processors at Computex 2025, which released on July 30, 2025. These processors succeed the Zen 4 "Storm Peak" lineup and feature up to 96 Zen 5 cores. The processors come in two variants—the consumer "Threadripper" models and the more expensive workstation "Threadripper PRO" variants, which support more memory channels and PCIe lanes.^[47]

Common features of Ryzen 9000 HEDT/workstation CPUs:

• Socket: sTR5.
• Threadripper CPUs support DDR5-6400 in quad-channel mode while Threadripper PRO CPUs support DDR5-6400 in octa-channel mode with ECC support.
• L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
• L2 cache: 1 MB per core.
• Threadripper CPUs support 80 PCIe 5.0 lanes (4 of which runs PCIe 4.0 mode to the chipset; and remaining are usually running as 48 PCIe 5.0 lanes plus 24 PCIe 4.0 lanes), while Threadripper PRO CPUs support 128 PCIe 5.0 lanes (4 of which runs in PCIe 4.0 mode to the chipset), and extra 8 PCIe 3.0 lanes. Some lanes support alternative mode of running SATA3.
• No integrated graphics.
• Fabrication process: TSMC 4nm FinFET.

Threadripper 9000 processors officially support up to 6400 MT/s DDR5 memory, a significant increase from 5200 MT/s in the previous generation.^[49]

AI 400 Series

AMD announced an initial lineup of 6 models of Ryzen AI 400 processors on March 2, 2024, including two Ryzen 5 and one Ryzen 7 models. Manufactured on a 4 nm process, the processors feature between 6 and 8 cores. ^[50] Common features of Ryzen AI 400 desktop APUs:^[51]

• Socket: AM5.
• All the CPUs support DDR5-5600 RAM in dual-channel mode in 2x1R and 2x2R configuration, but only DDR5-3600 for 4x1R and 4x2R.
• L2 cache: 80 KB per core.
• L2 cache: 1 MB per core.
• Includes integrated RDNA 3.5 GPU.
• Includes XDNA 2 AI Engine (Ryzen AI).
• Fabrication process: TSMC 4 nm FinFET.

Strix Point & Krackan Point

The Ryzen AI 300 series of notebook processors was announced on June 3, 2024. Codenamed Strix Point (for the high performance Ryzen AI 9 300 series) & Krackan Point (for the mid-range Ryzen AI 5 and 7 300 series), these processors are named under a new model numbering system similar to Intel's Core and Core Ultra model numbering. Strix Point features a 3rd-gen Ryzen AI engine based on XDNA 2, providing up to 50 TOPS of neural processing unit performance. The integrated graphics is upgraded to RDNA 3.5, and top-end models have 16 CUs of GPU and 12 cores of CPU, an increase from the maximum of 8 CPU cores on previous-generation Ryzen ultra-thin mobile processors.^[52] Notebooks featuring Ryzen AI 300 series processors were released on July 17, 2024.^[53]

Common features of Ryzen AI 300 notebook APUs:

• Socket: BGA, FP8 package type.
• All models support DDR5-5600 or LPDDR5X-8000 in dual-channel mode.
• All models support 16 PCIe 4.0 lanes.
• Native USB4 (40Gbps) Ports: 2
• Native USB 3.2 Gen 2 (10Gbps) Ports: 2
• iGPU uses the RDNA 3.5 microarchitecture.
• NPU uses the XDNA 2 AI Engine (Ryzen AI).
• Both Zen 5 and Zen 5c cores support AVX-512 using a half-width 256-bit FPU.
• L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
• L2 cache: 1 MB per core.
• Fabrication process: TSMC N4P FinFET.

Gorgon Point

Common features of Ryzen AI 400 notebook APUs:

• Socket: BGA, FP8 package type.
• All models support DDR5-5600 or LPDDR5X-8000 (LPDDR5X-8533 for 440, 450, 465, 470, 475 series) in dual-channel mode.
• All models support 16 PCIe 4.0 lanes.
• Native USB4 (40Gbps) Ports: 2
• Native USB 3.2 Gen 2 (10Gbps) Ports: 2
• iGPU uses the RDNA 3.5 microarchitecture.
• NPU uses the XDNA 2 AI Engine (Ryzen AI).
• Both Zen 5 and Zen 5c cores support AVX-512 using a half-width 256-bit FPU.
• L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
• L2 cache: 1 MB per core.
• Fabrication process: TSMC N4P FinFET.

Strix Halo

Strix Halo represented a major departure of previous multi-chiplet mobile processors. Strix Halo's CCD is actually not the same type of CCD used on regular Zen 5 desktop processors. Instead it features a unique "sea of wires" interconnect that replaces the previous infinity fabric. This change allowed for greater power efficiency but also greater design complexity. This type of interconnect is rumored to be on Zen 6, the next generation of AMD CPU microarchitecture.^[61][62]

Common features of Strix Halo mobile CPUs:^[63]

• Socket: BGA, FP 11 package type.
• All CPUs only support soldered LPDDR5X memory with a 256-bit memory bus.
• All CPUs support 16 lanes of PCIe 4.0 lanes.
• iGPU uses the RDNA 3.5 architecture.
• Fabrication process: TSMC N4P FinFET.

Fire Range

Common features of Ryzen 9000 Fire Range series:

• Socket: FL1.
• All models support dual-channel DDR5-5600 with a maximum capacity of 96 GB.
• All models support 28 PCIe 5.0 lanes.
• Native USB 3.2 Gen 2 (10 Gbps): 4.
• Native USB 2.0 (480 Mbps): 1.
• iGPU: AMD Radeon 610M (2 CU @ 2200 MHz).
• No NPU.
• Fabrication process: TSMC N4 FinFET (CCD) + TSMC N6 FinFET (I/OD).^[65]

Turin

Alongside Granite Ridge desktop and Strix Point mobile processors, the Epyc 9005 series of high-performance server processors, codenamed Turin, were also announced at Computex on June 3, 2024. It uses the same SP5 socket as the previous Epyc 9004 series processors, and will pack up to 128 cores and 256 threads on the top-end model. Turin will be built on a TSMC 4 nm process.^[66]

Common features of EPYC 9000 server processors:

• Socket: SP5.
• The CPUs support up to DDR5-6400 in 12 channel mode.
• Fabrication process: TSMC N4X.

Zen 5c

Zen 5c ("Prometheus") is a compact variant of the Zen 5 ("Nirvana")^[1] core, primarily targeted at hyperscale cloud compute server customers.^[67] It will succeed the Zen 4c ("Dionysus") and Zen 4 ("Persephone") core.^[1]