ARM Cortex-A12
32-bit multicore processor
From Wikipedia, the free encyclopedia
The ARM Cortex-A12 is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. It provides up to 4 cache-coherent cores. The Cortex-A12 is a successor to the Cortex-A9.[2]
- 1–4
| General information | |
|---|---|
| Designed by | ARM Holdings |
| Physical specifications | |
| Cores |
|
| Cache | |
| L1 cache | 32–64 KiB I, 32 KiB D |
| L2 cache | 256 KiB–8 MiB (configurable with L2 cache controller) |
| Architecture and classification | |
| Instruction set | ARMv7-A |
| Products, models, variants | |
| Product code name |
|
| History | |
| Predecessor | ARM Cortex-A9 |
| Successor | ARM Cortex-A17 |
ARM renamed A12 as a variant of Cortex-A17 since the second revision of the core in early 2014, because they were indistinguishable in performance.[3][4]
Overview
ARM claims that the Cortex-A12 core is 40 percent more powerful than the Cortex-A9 core.[5] New features not found in the Cortex-A9 include hardware virtualization and 40-bit Large Physical Address Extensions (LPAE) addressing. It was announced as supporting big.LITTLE,[6] however shortly afterwards the ARM Cortex-A17 was announced as the upgraded version with that capability.[7]
Key features of the Cortex-A12 core are:[8]
- Out-of-order speculative issue superscalar execution pipeline giving 3.00 DMIPS/MHz/core.
- NEON SIMD instruction set extension.
- High performance VFPv4 floating point unit.
- Thumb-2 instruction set encoding reduces the size of programs with little impact on performance.
- TrustZone security extensions.
- L2 cache controller (0-8 MB).
- Multi-core processing.
- 40-bit Large Physical Address Extensions (LPAE) addressing up to 1 TB of RAM.
- Hardware virtualization support.
