NCR/32
Microprocessor architecture and chipset
From Wikipedia, the free encyclopedia
The NCR/32 VLSI Processor family was a 32-bit microprocessor architecture and chipset developed by NCR Corporation in the early 1980s. Generally used in minicomputer systems, it was noteworthy for being externally microprogrammable.[1][2]
| General information | |
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| Marketed by | NCR Corporation |
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History
NCR announced the release of its NCR/32 architecture, comprising an initial four-chip set, in the third quarter of 1982.[3] The Central Processor Chip included an external microcode bus that let a designer create custom instructions for specific applications.
This feature was used to develop microcode that allowed the NCR/32 to emulate NCR's earlier mainframe computers, or an IBM System/370.[4]: 1–5
The design also enabled high-level languages, such as Prolog and polyFORTH, to be executed directly from custom instructions in the external microcontrol store.[5][6]
Both the NCR/32 processor and some products that used it have been called reduced instruction set computer (RISC) systems, although the description has been debated;[7][8][9] the original Berkeley RISC and Stanford MIPS research programs did not complete until 1984, and avoiding the use of microcode was one of the key RISC design principles.[10][11][12]
NCR used the processor architecture in certain models of their own computer systems, communications peripherals, and at least one board-level product.
Some of the designers of the NCR/32 left NCR for a new company, Celerity Computing, which used the NCR/32 in its own minicomputer designs, running a version of the University of California at Berkeley's Unix Release 4.2.[11][13]
Chipset
The chipset for the NCR/32 family includes the following devices:
- NCR/32-000 Central Processor Chip (CPC)
- NCR/32-010 Address Translation Chip (ATC)
- NCR/32-020 Extended Arithmetic Chip (EAC)
- NCR/32-500 System Interface Controller (SIC)
- NCR/32-580 System Interface Transmitter (SIT)
- NCR/32-590 System Interface Receiver (SIR)
Features
The NCR/32-000 CPC was the cornerstone of the architecture; all of the other devices were optional. The CPC consists of 40,000 transistors, and was originally fabricated in a 3 micron NMOS process. The device supports two levels of microcode: vertical microcode, stored in an external 128K-byte Instruction Storage Unit (ISU), and horizontal microcode, stored in an internal Read-only memory (ROM) encoding 179 operations in a set of 95-bit wide words. The CPC accesses the ISU over a 16-bit wide Instruction Storage Unit Bus (ISUBUS), feeding a 3-stage microinstruction pipeline. Internally, the CPC has a 32-bit wide Arithmetic Logic Unit (ALU), and 16 32-bit general purpose registers. The processor can address up to 4 GB of direct virtual memory, and 16 MB of direct real memory over a 32-bit wide Processor Memory Bus (PMBUS). The base clock frequency of the CPC is 13.3 MHz. With its two-phase, non-overlapping clock, each machine cycle takes two "ticks", yielding a cycle time of 150 nanoseconds (nS). 90% of the CPC's microinstructions complete in a single cycle.[1][4][14]
A revised version of the CPC was released later, with device geometry reduced from 3 to 2 microns[15] Cycle time on higher-performance NCR 10000 systems was down to 110 nS.[16]
The NCR/32-010 ATC provides advanced memory management services such as address translation, access protection, memory-refresh control, and error-checking and correction (ECC). It contains sixteen translation registers which handle mapping of 32-bit or 24-bit virtual addresses into 24-bit physical addresses, with page sizes of 1K, 2K, or 4K bytes.[4][14]
The NCR/32-020 EAC accelerates the execution of arithmetic operations, performing IBM-compatible single- and double-precision binary and floating-point arithmetic, packed and unpacked decimal storage, and format conversions.[14]
The NCR/32-500 SIC interfaces the PMBUS to slower peripherals and other systems. The NCR/32-580 SIT and NCR/32-590 SIR perform data format conversions. The SIC/SIT/SIR combination can operate in one of two modes: Data Link Control or Local Area Network.[14][1]
Applications
- NCR 9300 system.[10][15][17]
- NCR 9400 system.[15]
- NCR 9800 system.[18][19]
- NCR System 10000. Offering the Model 35, Model 55, Model 65, and Model 75 on release.[20][21][22][15] The Model 85 was released in early 1990.[10]
- NCR/32-796A Multibus single-board computer (SBC).[8][23]
- NCR Comten 5620 communications processor.[24]
- Celerity Computing used NCR/32 chips in various models, including their debut C1200, as part of their ACCEL architecture.[11]
- Honeywell signed an agreement with NCR to use the NCR/32 in its next-generation minicomputer, possibly the DPS-4.[25][26][27]