Open Verification Library

OVL works by placing modules or components checking specific properties of the circuit alongside regular modules or components. Those special modules are called checkers and are tied to circuit signals via ports. Some aspects of the checker functionality can be modified by adjusting checker parameters. Typical properties verified by OVL checkers include:

• condition that should be always met,
• sequence of conditions that should be met,
• condition that should never occur,
• proper data value (even, odd, within a range, etc.),
• proper value change (e.g. increment or decrement within specified range),
• proper data encoding (e.g. one hot or one cold),
• proper timing of event (within given number of clock cycles or within window created by trigger events),
• valid protocol of data transmission,
• valid behavior of popular building blocks (e.g. FIFOs).

Depending on the selected parameters, OVL checkers can work as assertion, assumption or coverage point checkers. Main source of OVL popularity is the fact that it allows introducing high-level verification concepts to the existing or new designs without requiring new language, e.g. a designer having access to Verilog tools does not need a new language to start using property checking with OVL.

While first versions of OVL supported Verilog and VHDL, most recent versions support (in alphabetical order):

• PSL - Verilog flavour
• SystemVerilog
• Verilog
• VHDL

Depending on the demand, support for two more languages may be added: PSL - VHDL flavour and SystemC.

• OVL section of the Accellera page