Talk:IBM System/370

@Guy Harris: Edit https://en.wikipedia.org/w/index.php?title=IBM_System/370&oldid=1153105243 changed a citation for the block multiplexor channel from section Types of Channels on pages 13-4 – 13-5 of PoOps to Start I/O Fast Release on pages 26-27. The new citation belongs on Start-I/O-Fast Queuing, not on the block mx channel. The original {{sfn}} should have specified the URL http://bitsavers.org/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf#page=355 for the -11 PoOps but was otherwise appropriate. The -0 PoOps does not include the relevant material, although a citation of the channel to CU OEMI^[1] would have been legitimate. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 12:16, 4 May 2023 (UTC)

So the problem is that IBM didn't give enough details about block multiplexor channels in the -0 PoOps? Guy Harris (talk) 19:06, 4 May 2023 (UTC)

I guess so - the first edition is, according to its cover, a manual that "describes extensions to the functional design of the System/360 that are incorporated in models of the System/370", so it's an addendum to a (sufficiently-recent) S/360 Principles of Operation, rather than a full independent Principles of Operation manual, as later editions (which had a lot more "extensions" to describe, such as "I haz MMUDAT box").

I'm not sure why they didn't describe block multiplexor channels, though. For what it's worth, the 2880 Block Multiplexor Channel was announced in February 1970 for the Models 85 and 195; the Model 85 was announce in 1968 and shipped in late 1969, so that was before the announcement of the first block multiplexor channel, and System/370 was announced in June 1970, which was after the announcement of the first block multiplexor channel. The block multiplexor channel appears to be mentioned in "IBM's 360 and Early 370 Systems" only in a footnote, and that book also speaks of S/370 being intended to come out in two phases, with phase 1 being a "small delta from S/360" (and a smaller delta from S/360 Model 85) phase and phase 2 being the larger "now with added DAT!" phase, so perhaps either 1) the block multiplexor channel was a late addition and there wasn't time to document it more fully, 2) they documented it in a manual about the 2880, or 3) they thought it wasn't important enough to mention in the first edition and deferred it to a later edition that was a stand-alone Principles of Operation for phrase 2.

In any case, I've updated the reference to point to the Eleventh Edition section describing block multiplexor channel operation. Guy Harris (talk) 10:04, 13 May 2023 (UTC)

Right pages, wrong section - I've corrected that. Meanwhile, I ran into a problem: {{snd}} was displaying what looked like an HTML character attribute; I'm assuming that under some circumstances it doesn't generate trailing semicolns. IAC, I used a - to bypass the problem. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 01:24, 14 May 2023 (UTC)

The statement The 390, which was based on a new ESA/390 model, expanded the multiple memory concept to include full hardware virtualization that allowed it to run multiple operating systems at the same time. is anachronistic; Virtual Machine Facility/370^[a] (VM/370) allowed running multiple operating systems on the same machine in 1972 and PR/SM on the 3090 offered similar support in 1988 as a processor option, while ESA/390 didn't come out until 1990.

There were certainly incremental improvements in PR/SM for S/390, but the basic capability had been around for two decades. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 17:55, 26 April 2024 (UTC)

Perhaps that's referring to the ESA/370 (not 390) interpretive-execution facility, with the SIE instruction. But even that wasn't a requirement to "run multiple operating systems at the same time"; that was done on boring old IBM System/360 Model 67 machines, with only the MMU and the privileged operation exception as hardware assists. Guy Harris (talk) 22:57, 5 May 2024 (UTC)

Maybe he was thinking of PR/SM, which looks as if it came out at the same time as ESA/370 on the "E" models of the IBM 3090. I think that's the first hypervisor that ran below the Principles of Operation+SIE etc. level, rather than running atop that level. But, again, that's ESA/370, not ESA/390. Guy Harris (talk) 23:09, 5 May 2024 (UTC)

Actually, the implementation of PR/SM on the 3090 has a custom version of CP running under the covers, and it uses SIE. — Preceding unsigned comment added by Chatul (talk • contribs) 14:30, 6 May 2024 (UTC)

unning under the covers That's what I meant by "running below...". "+SIE" means "I don't remember whether the Principles of Operation include SIE or not, and I'm too lazy to look it up in the ESA/370 Principles of Operation, so I'll add it."

Looking at the ESA/370 Principles of Operation on Bitsavers, it looks as if it mentions the interpretive-execution facility in passing and points the reader to IBM 370-XA Interpretive Execution, SA22-7095. It dates back to the 370-XA era, so it's not the feature that supports full hardware virtualization.

But I just noticed that what the article says is

The 390, which was based on a new ESA/390 model, expanded the multiple memory concept to include full hardware virtualization that allowed it to run multiple operating systems at the same time.

(italics mine). I'm not sure what "the multiple memory concept" is; about the only thing that comes to mind is the multiple address space concept. IBM Enterprise Systems Architecture § ESA/390 architecture says

A machine may be divided into Logical Partitions (LPARs), each with its own virtual system memory so that multiple operating systems may run concurrently on one machine.

which seems to suggest that LPARs are new with ESA/390. However, the ESA/390 Principles of Operation speaks of LPARs as having been introduced with ESA/370, so I'll fix that. Perhaps that's the source of the confusion. Guy Harris (talk) 18:56, 6 May 2024 (UTC)

The vast majority of the code in CP uses the instructions in PoOps, although in a few cases PoOps defines parameters to be model dependent. SIE has its own manual, and only the initial version is available to the general public.

BTW, does IBM consider PR/SM to be part of ESA? -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 16:13, 7 May 2024 (UTC)

SIE has its own manual, and only the initial version is available to the general public. So PR/SM may use some facility that's not a fully-specified part of the architecture.

BTW, does IBM consider PR/SM to be part of ESA? It doesn't appear to be mentioned in the first edition of the ESA Principles of Operation. However, the ninth edition of the ESA/390 Principles of Operation says, in the "The ESA/370 and 370-XA Base" section of Chapter 1, that

The facilities that were new in ESA/370 are as follows:

...

The Processor Resource/Systems Manager* (PR/SM*) feature provides support for multiple preferred guests under VM/XA and provides the logically partitioned (LPAR) mode, with the latter providing flexible partitioning of processor resources among multiple logical partitions. Certain aspects of the LPAR use of PR/SM are described in the publication IBM ES/3090 Processor Complex Processor Resource/Systems Manager Planning Guide, GA22-7123.

Perhaps a later edition of the ESA/370 Principles of Operation mentioned it as being part of the architecture.

The impression I have is that, starting at least with the 3090, there are layers of the architecture are implemented by "licensed internal" machine code (or whatever they've called it in the past), rather than hardware or microcode. The CMOS processors implement some instructions and facilities in millicode, and some processors had another layer atop that with "i370" or "i390" code (I've seen at least one mention to "i390" code in z/Architecture machines); PR/SM is, I think, another such layer. Guy Harris (talk) 17:24, 7 May 2024 (UTC)

Microcode, millicode and the version of CP used by PR/SM are all licensed internal code. Basically, any code loaded from the internal 3370 drives is LIC. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 09:05, 8 May 2024 (UTC)

Microcode, millicode and the version of CP used by PR/SM are all licensed internal code. As, presumably, is the i370/i390 code. I think i370 originated in a multichip microprocessor designed at IBM Böblingen for some 9370 models.^[1][2] i390 is presumably the equivalent for 390 machines; IBM appear not to have used "iz" or whatever for the z/Architecture machines, sticking with "i390".^[3][4][5] (I'd love to see the equivalent of datasheets for the various CMOS single-chip CPUs, indicating what happens on power-on reset, as well as an internal description of the LIC and the way it's loaded - is there a boot ROM?)

Basically, any code loaded from the internal 3370 drives is LIC. Or from the equivalent storage, e.g. flash memory on more modern machines. Guy Harris (talk) 18:19, 8 May 2024 (UTC)

@Guy Harris: The article briefly describes S/370-XA, ESA/370 and ESA/390; permalink/1283135009 removed the infobox fpr = footnote 16 FP registers in S/390 with the comment Given that IEEE floating point, and a 16-register floating-point register set, didn't show up until S/390, it's not clear why we need to talk about it here rather than in the ESA page. Should the infobox footnote be reinstated, and should there be a hatnote citing the XA and ESA pages. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 13:13, 31 March 2025 (UTC)

Briefly mentions S/370-XA, ESA/370 and ESA/390, and doesn't mention the expansion of the FP registers in later S/390 or the addition of IEEE floating-point support, so, again, I don't see why the FP extensions not made in S/370, S/370-XA, or ESA/370 - i.e., not mentioned in pages about any line or ISA with "370" in its name - need to be mentioned here.

If there were a page that would be the 8-bit-byte IBM mainframe equivalent of x86, covering the evolution of the instruction set architecture from the original S/360 all the way up to the latest z/Architecture, that page would mention the FP changes, along with the addition of DAT, XA 31-bit addressing, ESA address spaces (and their dual-address-space predecessors), 64-bit support, etc.. Pages for S/360, S/370, etc. could also exist, just as IA-32 and x86-64 exist along with x86 (there's no x86-16 page, though, just a redirect to x86). Guy Harris (talk) 19:35, 31 March 2025 (UTC)

A recent edit by Citation bot removed the URL from a citation^[1] with the comment Removed URL that duplicated identifier. Is that legitimate and what does it mean? -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 14:01, 26 August 2025 (UTC)

The edit comment means that the DOI currently sends you to the same URL as the url= parameter. Presumably the idea is that the DOI would be updated if the URL were to change, and so would be considered preferable to the URL. Guy Harris (talk) 18:27, 26 August 2025 (UTC)

That sounds plausible, but |doi= doesn't make the title a link. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 18:50, 26 August 2025 (UTC)

That's an issue to take up either at User talk:Citation bot (ask that it not do the removal of URLs that duplicate identifiers) or with the maintainers of various templates that include identifier parameters (ask that, if there's no url= parameter but there is an identifier parameter, the link for the identifier parameter value be used for the title as well).

An alternative would be to link to the (non-paywalled, at least for now) PDF for the "New Products" section of that issue of IEEE Computer, which also more directly takes the reader to the information; I've done that. Guy Harris (talk) 20:19, 26 August 2025 (UTC)