Talk:Z/Architecture
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Bad links
The links to "dataspaces" and "hiperspaces" can't be corrected so I removed them. If anyone wants to create appropriate pages feel free (and restore the links). Martin Packer (talk) 20:44, 19 May 2013 (UTC)
CPU register table
It would be nice to add a CPU register table for the Z architecture, similar to that shown for the S/370 and various other mainframe, mini, and microprocessor CPUs. — Loadmaster (talk) 17:49, 8 November 2016 (UTC)
Byte-addressable
The term byte-accessible, which had been used in the article now here as ==IBM mainframe expanded storage==
is not telling the whole story.
http://stackoverflow.com/questions/4504775/endianness-inside-cpu-registers
refers to a situation described as:
- "That's byte accessible, not byte "addressable'"
- (loading a word into a pair of registers and then accessing one byte in one of the registers)
The IBM addressing system has an ADDRESS for each byte!
Not a deciding vote, but... Dr. Google prefers byte-addressable to byte-accessible Pi314m (talk) 17:44, 25 January 2017 (UTC)
MVCL, MVPG atomic?
I'm puzzled by the statement that both MVPG and MVCL are atomic. I think MVCL has always been interruptible (from GA22-7000-10 for S/370, SA22-7832-00 for Z/Architecture; note 8 on MVCL in both references describes some bad scenarios), and therefore can be observed as partially complete even on a single CPU. MVPG is not interruptible, but the last paragraph of its description in SA32-7832-00 implies that it can be observed as partially executed by other CPUs and channel programs: "not necessarily performed in a left-to-right direction as observed by other CPUs and by channel programs." Clem Dickey (talk) 18:03, 17 October 2017 (UTC)
- Per above reference to 370 POP Note 8 (on p. 7-27 of GA22-7000-10), and after reviewing the Patent notes I cited in Z/Architecture, which highlights Dr. Google's disagreement with saying "Atomicity," it seems that using the diplomatic plural rather than "THE" to edit and mend/emend/amend non-compliance with:
- (From Greek "atomos", indivisible) Indivisible; cannot be split up (atomic from FOLDOC)
- a guarantee of isolation from interrupts, signals, concurrent processes and threads. (2nd sentence, Atomicity (programming), which redirects to Linearizability)
- an operation: guaranteed to complete either fully or not at all while waiting in a pause, and running synchronously when called by multiple asynchronous threads. (wiktionary: atomic, for computing)
- to read:
- These instructions do not comply with definitions for Atomic / AtomicAtomicity, although they can be used as a single instruction within documented timing and non-overlap restrictions.[1]{{rp|Note 8, page 7-27}}<ref>"things are done immediately, and there is no chance of the instruction being half-completed or of another being interspersed. Used especially to convey that an operation cannot be interrupted." {{cite web
|url=http://wwww.foldoc.org/atomic |title=Atomic from FOLDOC}}</ref>
- These instructions do not comply with definitions for Atomic / AtomicAtomicity, although they can be used as a single instruction within documented timing and non-overlap restrictions.[1]{{rp|Note 8, page 7-27}}<ref>"things are done immediately, and there is no chance of the instruction being half-completed or of another being interspersed. Used especially to convey that an operation cannot be interrupted." {{cite web
|url=http://wwww.foldoc.org/atomic |title=Atomic from FOLDOC}}</ref>
- Per above reference to 370 POP Note 8 (on p. 7-27 of GA22-7000-10), and after reviewing the Patent notes I cited in Z/Architecture, which highlights Dr. Google's disagreement with saying "Atomicity," it seems that using the diplomatic plural rather than "THE" to edit and mend/emend/amend non-compliance with:
- is a good idea. I will also add as "Further Reading" Preshing on Programming - Atomic vs. Non-Atomic Operations (http://preshing.com/20130618/atomic-vs-non-atomic-operations) and another item.
- My WP:OR on the matter is:
- Atomicity is only from a limited perspective, since an external probe operating at a higher speed can observe a before/early-stage_during/mid-stage_during/late-stage_during/after of an event that the processor under observation, to the extent that it has a say, says is atomic. MVCL, according to the Principles of Operation manual, does not allow the operands to overlap, hence "not necessarily performed in a left-to-right direction as observed by other CPUs and by channel programs" is not only permitted but often a good way to do things, especially compared to MVC-loops of decades past. Pi314m (talk) 19:05, 18 October 2017 (UTC)
- My WP:OR on the matter is:
References
- MOVE LONG, note 8. "GA22-7000-10, IBM System/370, Principles of Operation" (PDF).
s/390x
while s/390x redirects here, it is nowhere explained. s/390x and s/390 are two similar, but different things, this needs to be explained... --151.37.183.184 (talk) 17:57, 22 October 2018 (UTC)
- "s/390x" doesn't exist. s390x now redirects to Linux on IBM Z § Hardware, which mentions the Linuxisms "s390" and "s390x". Guy Harris (talk) 22:45, 22 April 2023 (UTC)
PSW et al
I'm slowly hacking away at fleshing out the articles, and one of the issues is where to put the narrative and diagrams for the PSW. The options are:
- Put PSW in a stand-alone section
- Put PSW directly under Architectural details
- Put PSW under Registers
- Put the PSW in the same table as the other registers
- Put the PSW in a table containing only long and short PSW
In addition to suggestions on how to handle the PSW, I'd appreciate any feedback on overall organization of the article And,of course, I'd apprciate anybody willing to do some of the writing. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 19:16, 26 June 2024 (UTC)
- Put it in the same table as the other registers, the same way it's done in IBM System/360 architecture, IBM System/370, IBM System/370-XA, and IBM Enterprise Systems Architecture. IBM System/370 shows both the BC and EC mode PSWs; this could probably do the same. Guy Harris (talk) 22:29, 26 June 2024 (UTC)
- OK. What about the narrative for the PSW and FPC register? -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 09:00, 27 June 2024 (UTC)
- PSW: z/Architecture should mention both long and short formats (and show them in the table), and describe the changes.
- FPC: the bulk of the narrative belongs in ESA/390, as it was (as I guessed, given that most other ISAs equivalent contain a bunch of control and status bits that deal with IEEE 754) introduced with the binary floating-point feature. That section of IBM Enterprise Systems Architecture should have a description of the new floating-point capabilities that showed up with the G5 processor - new registers (even for hex floating-point) and IEEE 754 support. z/Architecture should mention the further changes to that register - and the rest of the changes for decimal floating-point arithmetic. Guy Harris (talk) 10:28, 27 June 2024 (UTC)
- OK. What about the narrative for the PSW and FPC register? -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 09:00, 27 June 2024 (UTC)
Binary (IEEE) floating-point
I'd say that should be mentioned in ESA/390, along with finally increasing the number of FP registers to 16, as it was introduced there, not in z/Architecture. Guy Harris (talk) 20:54, 26 June 2024 (UTC)
- Done. Guy Harris (talk) 19:46, 30 June 2024 (UTC)
Architectural details of post-S/360 architectures
What architectural details should pages other than IBM System/360 architecture show? Changed or new details, or all, including stuff inherited from the predecessor architecture? Guy Harris (talk) 20:56, 26 June 2024 (UTC)
Help! Formatting error in register table
I've added another register to the register table, and the subtable title is rendered with a short width. Can anybody spot what I did wrong in BEAR? Thanks. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 17:56, 30 June 2024 (UTC)
- Not sure whether there's a simpler fix, but putting two 32-bit boxes, as is done for other 64-bit registers, seems to fix the problem. Guy Harris (talk) 19:45, 30 June 2024 (UTC)
Each CPU?
The sections about registers say that "Each CPU" has the register or set of registers in question. Is it clear that a "CPU" doesn't mean "a big cabinet containing multiple multi-core and possibly multi-threaded microprocessors" but "a CPU core" or, given that some (most?) z/Architecture processors are multithreaded, "a hardware thread in a CPU core"? Guy Harris (talk) 17:44, 1 July 2024 (UTC)
- I'm not sure of the best way to word things. Current models are virtual multiprocessors; when the multithreading feature is enabled; there are multiple CPUs in a core, sharing some circuitry. If the feature is not installed, or is disabled, then CPU is synonymous with core. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 19:38, 1 July 2024 (UTC)
Vector facility
Currently IBM z13 § Vector Facility has a brief description of the vector facility, which is not replicated in the articles for later processors. I believe that it would be better to add a vector facility section to z/Architecture and to link to that from z13 on. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 10:56, 6 January 2025 (UTC)
- Given that the vector facility is described in the Principles of Operation, it definitely belongs here, not in a page for any particular processor. Guy Harris (talk) 20:44, 6 January 2025 (UTC)
- hi guy, hi chatul, I did the read-thru and analysis of z-Architecture and the IBM 370 techref, and put the results on the BP talk page. zA is not Vector it is SIMD-within-a-Register, it doesn't have predicate masks either so is PACKED SIMS, not PredicatedSIMD. Talk:Vector_processor yes this is really confusing and weird, but ultimately is Marketing Material. I can see vestiges of names of registers from the 370, and they tried to keep the Load-with-length but they did it by merging a 128-bit LD instruction with an extra operand: the number of elements. it's a half-baked idea that saves some bytes. Lkcl (talk) 13:26, 24 July 2025 (UTC)
- There's IBM's term for the z/Architecture feature, "Vector Facility", and there's whether the IBM term is accurate. We should use IBM's term, even if it's inaccurate, but, if it's not what's generally thought of as what a vector processor does, we should use "vector" only in the name of the facility, and should note the difference. Guy Harris (talk) 14:55, 24 July 2025 (UTC)
- hi guy, hi chatul, I did the read-thru and analysis of z-Architecture and the IBM 370 techref, and put the results on the BP talk page. zA is not Vector it is SIMD-within-a-Register, it doesn't have predicate masks either so is PACKED SIMS, not PredicatedSIMD. Talk:Vector_processor yes this is really confusing and weird, but ultimately is Marketing Material. I can see vestiges of names of registers from the 370, and they tried to keep the Load-with-length but they did it by merging a 128-bit LD instruction with an extra operand: the number of elements. it's a half-baked idea that saves some bytes. Lkcl (talk) 13:26, 24 July 2025 (UTC)
IEEE 754 decimal floating point
Should the format of floating point registers in decimal format go in a new § Decimal-floating point or in the main register chart, which is already very large? Should the new section describe related features. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 12:17, 4 July 2025 (UTC)
- Maybe no page about an architecture that implements IEEE 754 floating point should show the format of the floating-point registers:
- For binary, they could point to Single-precision floating-point format § IEEE 754 standard: binary32 for the single-precision format and Double-precision floating-point format § IEEE 754 double-precision binary floating-point format: binary64 for the double-precision format.
- For decimal, perhaps Decimal floating point § IEEE 754-2008 encoding should have a diagram showing the formats, to which architecture pages can point.
- Perhaps there should be a page or pages dedicated to the 754 format.
- Pages for various S/3x0 architectures can also point to IBM hexadecimal floating-point § Single-precision 32-bit, IBM hexadecimal floating-point § Double-precision 64-bit, and IBM hexadecimal floating-point § Extended-precision 128-bit. Guy Harris (talk) 18:32, 4 July 2025 (UTC)
Revision of the ISA?
@Lkcl: Is it appropriate to refer to revisions of the ISA rather than to editions of the Principles of Operations manual? IBM has never suggested a strict correlation between the two and implying one might be OR. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 16:52, 7 August 2025 (UTC) -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 16:52, 7 August 2025 (UTC)
- IBM appears to have had some "ARCHLVL n" values, but 1) those only date back, I think, to System/390, not all the way back to System/360 and 2) n is not the version number of the corresponding edition of the Principles of Operation.
- It's probably best to refer to editions of the Principles of Operation as such rather than as versions of the ISA. Guy Harris (talk) 20:23, 7 August 2025 (UTC)
- ARCHLVL is tied to software reqirements and sometimes skips over multiple hardware generations. I'd recommend language like
First documented in edition foo of the Principles of Operation manual.
-- Shmuel (Seymour J.) Metz Username:Chatul (talk) 22:42, 7 August 2025 (UTC)ARCHLVL is tied to software reqirements and sometimes skips over multiple hardware generations.
x86-64 § Microarchitecture levels describes something for x86-64 that sounds similar. Guy Harris (talk) 23:30, 7 August 2025 (UTC)- that means tracking down each revision and reading the index of each! Lkcl (talk) 23:42, 7 August 2025 (UTC)
- It's worse than that. PoOps describes facilities, e.g., Distinct-Operands Facility, but it doesn't say what processor or generation added the facility. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 12:51, 8 August 2025 (UTC)
- At least the z/Architecture Principles of Operations manuals have introductory sections (in the Roman-numeraled pages) that list changes made in various editions, although that still doesn't say anything about hardware or any official generations of the architecture. Guy Harris (talk) 20:55, 8 August 2025 (UTC)
- It's worse than that. PoOps describes facilities, e.g., Distinct-Operands Facility, but it doesn't say what processor or generation added the facility. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 12:51, 8 August 2025 (UTC)
- ARCHLVL is tied to software reqirements and sometimes skips over multiple hardware generations. I'd recommend language like
- (thank you to everyone chipping in. here - the issue came up in the new page I created, Bit_manipulation_instruction_set. I got to z/Architecture via the IBM 3090 I think, and went "hang on a minute, this is Cray-style vectors, moo? I thought z13 was Altivec/PackedSIMD??" and sure enough I found I had SA22-7832-10 and -13 PDFs, one 11th edition and the other 15th and will need to have both in the bmisa page. this illustrates that not mentioning the change is Historically misleading. and will confuse the heck out of z/Architecture users :) Lkcl (talk) 23:38, 7 August 2025 (UTC)
- I'm happy with whatever others decide, here, as long as it does not mislead (historically accurate). exact wording. I am easy, happy to take a back seat. Lkcl (talk) 23:41, 7 August 2025 (UTC)
z/Architecture Principles of Operation editions I've found:
- https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr000.pdf - 1st
- https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr001.pdf - 2nd
- https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr002.pdf - 3rd
- https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr003.pdf - 4th
- 5th and 6th aren't at the obvious URLs
- https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr006.pdf - 7th
- https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr007.pdf - 8th
- https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr008.pdf - 9th
- https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr009.pdf - 10th
- https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr010.pdf - 11th
- https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr011.pdf - 12th
- 13th not at either of the obvious URLs
- https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-7832-13.pdf - 14th
- https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-7832-14.pdf - 15th
There are also some other versions at vm.ibm.com:
- https://www.vm.ibm.com/library/other/22783211.pdf - 12th
- https://www.vm.ibm.com/library/other/22783212.pdf - 13th
- https://www.vm.ibm.com/library/other/22783213.pdf - 14th
but not the earlier ones or the 15th.
And, in another obscure corner of the IBM library, we have:
- https://www.ibm.com/support/pages/sites/default/files/inline-files/SA22-7832-00.pdf - 1st
- https://www.ibm.com/support/pages/sites/default/files/inline-files/SA22-7832-01.pdf - 2nd
- 3rd isn't at the obvious URL
- https://www.ibm.com/support/pages/sites/default/files/inline-files/SA22-7832-03.pdf - 4th
but nothing later. Guy Harris (talk) 21:38, 8 August 2025 (UTC)
- Maybe restructure as
- Notes
- Explanatory notes
- Editions of Principles of Operation - with an anchor - formatted as definition list with
|ref={{sfnref | editionref}} - References
- Notes
- At this time, https://www.ibm.com/docs/en/ seems to be where IBM parks things; I believe that there is a shorter fragment than docs/en/module_1678991624569/pdf/ that will work. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 14:16, 10 August 2025 (UTC)
- @Guy Harris: I've added every edition for which you provided a URL to the beginning of § References. Note that the revision suffix is one off from the edition numbers. My naming convention is that z-foo is revision foo edition foo+1 and z is the most recent edition; go ahead and change it if you think a better convention should be used. I also corrected the first appearance of the vector facility, added
|loc=Summary of Changes in Eleventh Editionand added a page URL. - Do you think the list of editions should be split into a separate section or subsection? -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 10:27, 12 August 2025 (UTC)
My naming convention is that z-foo is revision foo edition foo+1
That's the same convention used by the publisher (for their documents, SAnn-nnnn-00 is the first edition, SAnn-nnnn-01 is the second edition, etc.), so that makes sense.Do you think the list of editions should be split into a separate section or subsection?
That might make sense - it's a pretty big list, and moving it to "Principles of Operation editions", or whatever, wouldn't affect {{sfn}}.- BTW, what's the difference between z-foo and just z? If there were a URL that went to the current edition, that might make sense for use z, but, as far as I know, there isn't - plus, page numbers aren't guaranteed to to work with such a link. Guy Harris (talk) 18:45, 12 August 2025 (UTC)
- The IBM rules for form codes are a bit more complicated: xynn-nnnn-rr, where the rules derive from the dead tree era:
- x
- Sales category
- G
- Free in reasonable quantities
- L
- Only available to licensees
- S
- Chargeable
- Z
- IBM internal use only
- y
- Usually A, C, F, G, H, R, X, or Y
- y-nn-nnnn
- Uniquely identifies the publication. Each n is a decimal digit.
- rr
- Identifies a specific edition, with -0 being the first edition.
- It hadn't occurred to me that page numbers may not be stable across editions. Given that, we should probably get rid of the z anchor and just use z-foo or some equivalent. --Shmuel (Seymour J.) Metz Username:Chatul (talk) 21:11, 12 August 2025 (UTC)
The IBM rules for form codes are a bit more complicted
Yeah, I just put "SA" in there as that's what was used for the z/Architecture Principles of Operation documents; I knew there were other sequences, I just didn't know what the code was - thanks for explaining the sales category letter. (I remember some older documents without it.- Any idea what the letter after it was? I think Y tended to be used for internal or internals documents such as PLMs. Was A more for hardware (for some definition of "hardware") and C more for software? Guy Harris (talk) 23:56, 12 August 2025 (UTC)
- I simplified somewhat; the convention evolved over time. It was originally nn-nnnn-rr, the somewhere in the late 1950s a letter was added to make it ynn-nnnn-rr and in the late 1960s another letter was added to make it xynn-nnnn-rr. Off the top of my head, y may be:
- 2
- I've seen it for both hardware and software.
- 3
- I've seen it for both hardware and software.
- A
- Hardware
- C
- Software
- E
- Application
- F
- Bibliography
- Summary
- H
- Application
- L
- Custom, special and RPQ?
- N
- Technical News Letter (TNL), pages to update a base publication
- P
- Programming announcement?
- R
- Course
- Handbook
- Hardware and software logic
- X
- Handbook
- Reference summary
- Template
- Y
- Logic
- Systems
- I don't recall the letter for coding forms. And there may be many others, but they haven't been discovered. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 08:15, 13 August 2025 (UTC)
- I simplified somewhat; the convention evolved over time. It was originally nn-nnnn-rr, the somewhere in the late 1950s a letter was added to make it ynn-nnnn-rr and in the late 1960s another letter was added to make it xynn-nnnn-rr. Off the top of my head, y may be:
- The IBM rules for form codes are a bit more complicated: xynn-nnnn-rr, where the rules derive from the dead tree era:
Edition tags for Principles of Operation
I used the label "Z-n" for SA22-7832-n, edition n+1, of z/Architecture Principles of Operation, with an anchor of |ref={{sfnref | Z-n}}. It's short, but it may not have been as obvious as I hoped. Would either of "Z/Architure ed. n+1"[a] or "SA22-7832-n" be better? -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 12:33, 25 August 2025 (UTC)
Notes
- I don't know whether the embedded blanks are legitimate, but the seem to work.