Talk:ZX Spectrum graphic modes

The article says under ZX Spectrum graphic modes#Graphics memory structure and pixel coordinates:

The address bitpattern contains two more bitpattern transpositions than necessary. The fastest and the simplest bitpattern would have been 0, 1, 0, x7, x6, x5, x4, x3, y7, y6, y5, y4, y3, y2, y1, y0, which makes the pixel addresses increase by the column first. Unfortunately, the ZX Spectrum designers were working under extreme time pressure, and failed to notice this simple improvement.

I do not have access to the cited book on ULA, but this statement ist at least incomplete. Given the Spectrum’s resolution of 256x192, the proposed bitpattern would leave 1/4 of the video memory unused: Each 192 bytes (corresponding to one column of 8 pixel width) would be followed by 64 unused bytes.

If the Spectrum’s resolution could have been made 320x256 instead, the proposed bitpattern might have worked well. (I am not sure because of timing and 66% higher video memory usage.) But then the article should say so. Spheniscus (talk) 19:41, 11 May 2025 (UTC)

The proposed bitpattern is 16 bits wide, of which the last 13 bits are affected by coordinates (x, y). Those 13 bits can address exactly 2^13 = 8 KiB of RAM.

Yes, that leaves a quarter of those 8 KiB supposedly “unused,” although color attributes or various BASIC and system variables could have easily been placed in the 64-byte gaps. The bitpattern is faster because it involves fewer transpositions, requiring less shifting and bitmasking when computing pixel addresses, at the expense of less than 2 KiB of RAM lost to gaps.

In modern computer systems, there is a similar feature, where the screen pitch (let’s say 2048 pixels) is typically wider than the visible screen width (let’s say 1920 pixels). The remaining pixels after line ends are unused. 95.178.134.236 (talk) 10:34, 5 August 2025 (UTC)

PS: Your "66% higher video memory usage" is an incorrect statement. Also, the proposed bitpattern actually requires minimal changes to the ULA, even with attributes placed in the "gaps". There is no reason why it couldn't work. 95.178.134.236 (talk) 10:53, 5 August 2025 (UTC)

The Spectrum doesn't have 16K of "display memory". It's actually around 8K. In 16K models, that 16K is all there is, programs use the remaining 8K-or-so for code. The first half of the RAM is display memory, the rest isn't. So claiming you can write to "display memory" from 16384 to 32767 is just wrong.

And yes, most of this article looks like original research, bad research at that.

2A00:23C5:2E2:1A01:B2:618A:DA6A:6FF5 (talk) 11:21, 21 August 2025 (UTC)

There are two buses visible on the original ZX Spectrum schematics. They are unnamed there, but can be called the "graphics memory bus" and the "main memory bus." The graphics memory bus connects directly to the ULA, while the main memory bus connects to the CPU. The two buses can operate in parallel. The schematics show that the two busses are joined (or separated) by a bus bridge. Because the 16K memory chips sit on the bus directly connected to the ULA and not directly to the CPU, those chips meet the usual definition of discrete graphics memory. ~2025-33460-31 (talk) 03:41, 14 November 2025 (UTC)

That's not quite so.The bus bridge is just a bunch of resistors that connect the two busses together such that when there is a bus contention, the ULA wins. There is no other form of bus access resolution. Those 16kB of memory are the computer's main (and only, for the 16k Spectrum) memory and this memory is shared with the ULA - which is not exactly a graphic controller. So no, the Spectrum does not have 16K of display memory. It has 16K (to 48K) of system memory, of which 32 x 192 (bitmap) + 32 x 24(attributes) (a total of 6912 bytes) represents the display file (that can be saved as such with the SAVE SCREEN$ command or replaced with LOAD SCREEN$). Apass ~2025-42208-83 (talk) 17:28, 23 December 2025 (UTC)

The bus bridge is implemented with resistors on the data lines and 2×4-bit multiplexers on the address lines. Apparently, you agree that there are two busses on the mainboard.

They indeed are two separate buses functionally: both can operate simultaneously, showing they’re separate buses.

The ULA is the Spectrum’s graphics controller (it also handles other I/O); most ULA logic gates are dedicated to display/graphics.

CPU access to ULA-connected memory doesn’t change its classification: a memory block is “graphics” based on which bus it’s connected to, not whether the CPU can read/execute it.

By your logic, all modern GPUs have only 8 MB of graphics memory because that is the size of the frame-buffer displayed on screen? Of course not, because the "graphics memory" are the chips directly connected to the GPU, not just the part that gets displayed. ~2025-42507-90 (talk) 16:08, 25 December 2025 (UTC)

Yes. The whole mumbo-jumbo about 16K of video memory / 32K (????) of system memory must go. By that definition, the 16K Spectrum has no system memory?? Apass ~2025-42208-83 (talk) 18:16, 23 December 2025 (UTC)

On 16K Spectrums there are no DRAM chips fitted to the main-CPU bus, but that doesn’t mean the main bus is absent. All 16K machines can be upgraded with 32K on the main bus, which then becomes active.

There is no concept of “system memory” in the docs, as far as I can remember. The 16K DRAM block is called “contended memory” in the documentation. Contended memory is connected directly to the graphics controller (the ULA) and only indirectly to the CPU via the bus bridge — therefore it functions as graphics memory. ~2025-42507-90 (talk) 16:08, 25 December 2025 (UTC)

But by the same token, there is no graphics memory either. What you say that contented memory is graphics memory is, in fact, your conclusion, so it is original research, not supported by any source connected to the official documentation. And like I said, the ULA is not a graphic controller. You can search any documentation from Sinclair and you will not find such a definition. The ULA also generates the CPU clock, the frame interrupt, handles the input / output ports (e.g. for tape loading and saving). The clock generator is a critical function without which the Spectrum would be a brick. Yes, the ULA handles the video output of the Spectrum, and that handling occupies a large area, but it was never called a graphics controller.

The 16kB which contain the display file are a shared resource for the CPU and for the ULA. A simultaneous access of the data bus by the CPU and by the ULA will lead to a Bus contention which is solved only by controlling the drive strengths of the data outputs of the CPU (via the resistors), hence, the memory is contended.

From a computer's perspective, the contented memory behaved as any other memory, fully integrated in the normal RAM space address range, and there were programs that used it as such (especially copiers). Apass ~2025-42208-83 (talk) 18:23, 25 December 2025 (UTC)

The ULA is the graphics controller. Since the Spectrum has graphics, there must be a controller somewhere. If it is not the ULA, then find me the circuit that serves as the graphics controller. The ULA being an I/O and keyboard controller does not preclude it also being a graphics controller.

The 16 KB contention is solved by the ULA cutting off the Z80 CPU’s clock signal, pausing the CPU. The ULA then drives the bus with a stronger signal than the paused CPU can assert through the resistors. The CPU must be paused first, otherwise it would read incorrect data (i.e. the data which the ULA has requested). The ULA always has higher priority when accessing the 16 KB RAM and will pause the CPU whenever required.

It doesn’t matter that official docs never used the term “graphics controller.” What matters is how it was commonly called and perceived. “System memory” was an unusual, ill-defined term for the ZX Spectrum (and for many computers). “Graphics memory” was a common term in that era, and it’s extremely unlikely the 16 KB block was not commonly referred to as “graphics memory.”

The contended memory does not behave like other memory on the Spectrum because timings differ and can be partially unpredictable due to the ULA frequently reading it. Therefore timings differ significantly compared to CPU access to main RAM or ROM. That’s why it was very difficult, if not impossible, to write a tape-loading routine that runs from contended memory (loader routine ran from ROM instead).

When you said “the contended memory behaved as any other memory” you likely meant the CPU can access it. But that misses the point: “graphics memory” is simply RAM connected to the graphics circuitry. It doesn’t matter whether the CPU can also access those DRAM chips; they are still graphics memory because they are connected to the graphics controller directly and to the CPU indirectly. ~2025-43027-23 (talk) 03:01, 28 December 2025 (UTC)

Also, the word "discrete" in "discrete memory" comes from Latin and means "separate," as in: separated by a bridge. ~2025-42507-90 (talk) 17:01, 25 December 2025 (UTC)