User:ScotXW/amdgpu

• https://www.x.org/wiki/RadeonFeature/#index5h2

There are three different Device Dependent X (DDX)-drivers available:

• xf86-video-ati = the old proprietary DDX driver; works on top of fglrx.ko in parallel with the proprietary OpenGL driver.
• xf86-video-radeon = the FOSS DDX driver in Mesa; works on top of /drm/radeon
• xf86-video-amdgpu = the FOSS DDX driver by AMD; works in top of /drm/amd/amdgpu in parallel with proprietary OpenGL driver and with Mesa; uses Glamor!

The interface libraries for amdgpu are libdrm_generic and libdrm_amdgpu, cf. https://lwn.net/Articles/654542/.

cf. Free_and_open-source_graphics_device_driver#ATI.2FAMD, Graphics Core Next, commons:Category:Diagrams illustrating AMD technology

• Note: AMD publishes 3D shader and command queue documentation, AMD does do NOT publish register docs for recent GPUs. Information:
• https://fail0verflow.com/media/33c3-slides/index.html#/74
• https://www.x.org/wiki/RadeonFeature/#index5h2
• https://wiki.gentoo.org/wiki/AMDGPU
• drivers/gpu/drm/amd/include/asic_reg/
  • bif = Bus InterFace (implements i.a. the PCI Express endpoint)
  • dce = Display Controller Engine (this actually received an own brand-name: AMD Eyefinity)
  • gca = Graphics and Compute Array
  • gmc = Graphics Memory Controller (implements i.a. the GDDR5 SDRAM/HBM controller)
  • oss = Operating System Services
  • smu = System Management Unit (includes a LatticeMico32, fulfills system management and power management tasks)
  • uvd = Unified Video Decoder
  • vce = Video Coding Engine

For more statistics see e.g. heise.de and of course the man page for git.

Commands are sent to the GPU by putting them in rings:

• Graphics ring
• Compute rings
• DMA rings (seem to be only GCN 1.1 aka GCN 2nd aka Bonaire, Hawaii and newer)

Commands are processed by the GPU Command Processor. It contains multiple sub-units (ME (Micro Engine), PFP (Prefetch Parser), CE (Constant Engine), DE (Dispatch Engine)), each of which is a custom ‘F32’ CPU running microcode firmware. Rings can call out to Indirect Buffers (IBs) with more commands

GCN 1:

All resource descriptors (sometimes called “fetch constants” on previous hardware) are read from memory instead of registers. In order to improve performance, the CP block adds a new constant engine. The constant engine (CE) runs in parallel to the 3D engine, and allows constants to be written to memory ahead of the main command stream.

Updating Shader Resource Descriptors (SRDs) using the CPU would be too slow. The CP provides a constant update engine to accelerate the process.

PM4 is the packet API used to program the GPU to perform a variety of tasks. The driver does not write directly to the GPU registers to carry out drawing operations on the screen. Instead, it prepares data in the format of "PM4 Command Packets" in either system or video (a.k.a. local) memory, and lets the Micro Engine to do the rest of the job.

There are two CP engines on SI: the Constant Engine (CE) and the Drawing Engine (DE). Previous ASICs only had a DE (previously referred to as the Micro-Engine or ME). Certain packets are only allowed on the DE or the CE. Packets can be executed in the DE via the ring or via an INDIRECT_BUFFER packet. Packets can only be executed on the CE by using the INDIRECT_BUFFER_CONST packet.

• Draw Engine (DE): The standard graphics engine is now referred to as the Draw Engine. Most PM4 commands continue to be submitted to the DE command buffer.
• Constant Engine (CE): The constant engine uses a second, separate command buffer to control constant uploads. The engine runs in parallel with the draw engine, allowing constant updates to get sufficiently ahead of the draws/dispatches that will use them. Additionally, CP has 64KiB of on-chip RAM (CE RAM) that acts as a staging buffer for constant updates. Shaders cannot read directly from the CE RAM.

The 64KiB is carved up between the 3 rings, with ring-0 (gfx) having 32KB. The driver is responsible for further subdividing the partitions to store an on-chip copy of the most up-to-date copy of every SRD.

There are two CP engines on GCN 1.0 (SI, Southern Island): the Constant Engine (CE) and the Drawing Engine (DE). Previous ASICs only had a DE (previously referred to as the Micro-Engine or ME).

The purpose of this packet is to provide a generic and flexible way for the CP to write n Dwords of data to any destination to which it has access. As applicable, the writes can be sent from the CE, PFP, ME or DE (Dispatch Engine). The CE (and PFP) are limited to the GRBM (Graphics Register Backbone Manager) and MC (memory controller?) as destinations.

Note: The split between SRBM and GRBM is mostly between "3D engine" and "everything else" – register writes to the 3D engine need to be synchronized with the data flowing through the engine so the register logic is *really* complicated. The rest of the registers don't need to be pipelined and so are managed by a separate block. Most graphics/3D registers sit behind a FIFO, while other (display/asic setup/config) registers do not.

Hardware

Note: The following tables refer always to the most current stable Linux kernel version, i.e. support for Polaris is available only since Linux kernel 4.7 and not present in earlier versions!

The following table shows features of AMD/ATI's GPUs (see also: List of AMD graphics processing units).

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More information Name of GPU series, Wonder ...

Name of GPU series	Wonder	Mach	3D Rage	Rage Pro	Rage 128	R100	R200	R300	R400	R500	R600	RV670	R700	Evergreen	Northern Islands		Southern Islands	Sea Islands	Volcanic Islands	Arctic Islands/Polaris	Vega	Navi 1x	Navi 2x	Navi 3x	Navi 4x
Released	1986	1991	Apr 1996	Mar 1997	Aug 1998	Apr 2000	Aug 2001	Sep 2002	May 2004	Oct 2005	May 2007	Nov 2007	Jun 2008	Sep 2009	Oct 2010	Dec 2010	Jan 2012	Sep 2013	Jun 2015	Jun 2016, Apr 2017, Aug 2019	Jun 2017, Feb 2019	Jul 2019	Nov 2020	Dec 2022	Feb 2025
Marketing Name	Wonder	Mach	3D Rage	Rage Pro	Rage 128	Radeon 7000	Radeon 8000	Radeon 9000	Radeon X700/X800	Radeon X1000	Radeon HD 2000	Radeon HD 3000	Radeon HD 4000	Radeon HD 5000	Radeon HD 6000		Radeon HD 7000	Radeon 200	Radeon 300	Radeon 400/500/600	Radeon RX Vega, Radeon VII	Radeon RX 5000	Radeon RX 6000	Radeon RX 7000	Radeon RX 9000
AMD support
Kind	2D		3D
Instruction set architecture	Not publicly known										TeraScale instruction set						GCN instruction set					RDNA instruction set
Microarchitecture	Not publicly known					GFX1		GFX2			TeraScale 1 (VLIW5) (GFX3)			TeraScale 2 (VLIW5) (GFX4)	TeraScale 2 (VLIW5) up to 68xx (GFX4)	TeraScale 3 (VLIW4) in 69xx [7][8] (GFX5)	GCN 1st gen (GFX6)	GCN 2nd gen (GFX7)	GCN 3rd gen (GFX8)	GCN 4th gen (GFX8)	GCN 5th gen (GFX9)	RDNA (GFX10.1)	RDNA 2 (GFX10.3)	RDNA 3 (GFX11)	RDNA 4 (GFX12)
Type	Fixed pipeline[a]						Programmable pixel & vertex pipelines				Unified shader model
Direct3D	—N/a		5.0	6.0		7.0	8.1	9.0 11 (9_2)	9.0b 11 (9_2)	9.0c 11 (9_3)	10.0 11 (10_0)	10.1 11 (10_1)		11 (11_0)			11 (11_1) 12 (11_1)	11 (12_0) 12 (12_0)			11 (12_1) 12 (12_1)		11 (12_1) 12 (12_2)
Shader model	—N/a						1.4	2.0+	2.0b	3.0	4.0	4.1		5.0			5.1	5.1 6.5			6.7				6.8
OpenGL	—N/a			1.1	1.2	1.3		1.5[b][9]			3.3			4.5 (Windows), 4.6 (Linux Mesa 25.2+)[10]			4.6[11][c]
Vulkan	—N/a															1.1[c][d]	1.3[12][e]		1.4[13]
OpenCL	—N/a										Close to Metal		1.1 (not supported by Mesa)	1.2+ (on Linux: 1.1+ (no Image support on Clover, with Rusticl) with Mesa, 1.2+ on GCN 1.Gen)				2.0+ (Adrenalin driver on Win 7+) (on Linux ROCm, Mesa 1.2+ (no support in Clover, only Rusticl, Mesa, 2.0+ and 3.0 with AMD drivers or AMD ROCm), 5th gen: 2.2 win 10+ and Linux RocM 5.0+				2.2+ and 3.0 Windows 8.1+ and Linux ROCm 5.0+ (Mesa Rusticl 1.2+ and 3.0 (2.1+ and 2.2+))[14][15][16]
HSA / ROCm	—N/a																					?
Video decoding ASIC	—N/a										Avivo/UVD	UVD+	UVD 2	UVD 2.2	UVD 3		UVD 4	UVD 4.2	UVD 5.0 or 6.0	UVD 6.3	UVD 7 [17][f]	VCN 2.0 [17][f]	VCN 3.0 [18]	VCN 4.0	VCN 5.0
Video encoding ASIC	—N/a																VCE 1.0	VCE 2.0	VCE 3.0 or 3.1	VCE 3.4	VCE 4.0 [17][f]
Fluid Motion [g]																								?
Power saving	?										PowerPlay				PowerTune		PowerTune & ZeroCore Power					?
TrueAudio	—N/a																	Via dedicated DSP		Via shaders
FreeSync	—N/a																	1 2
HDCP[h]	—N/a										?							1.4		2.2		2.3 [19]
PlayReady[h]	—N/a																			3.0		3.0
Supported displays[i]						1–2	2							2–6								?			4
Max. resolution	?													2–6 × 2560×1600			2–6 × 4096×2160 @ 30 Hz			2–6 × 5120×2880 @ 60 Hz	3 × 7680×4320 @ 60 Hz [20]	7680×4320 @ 60 Hz PowerColor		7680x4320 @165 Hz	7680x4320
/drm/radeon[j]																			—N/a
/drm/amdgpu[j]	—N/a																	Optional [21]

Close

1. [a]

   The Radeon 100 Series has programmable pixel shaders, but do not fully comply with DirectX 8 or Pixel Shader 1.0. See article on R100's pixel shaders.
2. [b]

   R300, R400 and R500 based cards do not fully comply with OpenGL 2+ as the hardware does not support all types of non-power of two (NPOT) textures.
3. [c]

   OpenGL 4+ compliance requires supporting FP64 shaders and these are emulated on some TeraScale chips using 32-bit hardware.
4. [d]

   Vulkan support is theoretically possible but has not been implemented in a stable driver.
5. [e]

   Vulkan support in Linux relies on the amdgpu kernel driver which is incomplete and not enabled by default for GFX6 and GFX7.
6. [f]

   The UVD and VCE were replaced by the Video Core Next (VCN) ASIC in the Raven Ridge APU implementation of Vega.
7. [g]

   Video processing for video frame rate interpolation technique. In Windows it works as a DirectShow filter in your player. In Linux, there is no support on the part of drivers and / or community.
8. [h]

   To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
9. [i]

   More displays may be supported with native DisplayPort connections, or splitting the maximum resolution between multiple monitors with active converters.
10. [j]

    DRM (Direct Rendering Manager) is a component of the Linux kernel. AMDgpu is the Linux kernel module. Support in this table refers to the most current version.

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).

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More information Platform, High, standard and low power ...

Platform			High, standard and low power														Low and ultra-low power
Codename	Server	Basic						Toronto
		Micro																Kyoto
	Desktop	Performance													Raphael	Phoenix
		Mainstream	Llano	Trinity	Richland	Kaveri	Kaveri Refresh (Godavari)	Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir	Cezanne
		Entry
		Basic																Kabini				Dalí
	Mobile	Performance										Renoir	Cezanne	Rembrandt	Dragon Range
		Mainstream	Llano	Trinity	Richland	Kaveri		Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir Lucienne	Cezanne Barceló			Phoenix
		Entry																				Dalí			Mendocino
		Basic															Desna, Ontario, Zacate	Kabini, Temash	Beema, Mullins	Carrizo-L	Stoney Ridge		Pollock
	Embedded			Trinity		Bald Eagle		Merlin Falcon, Brown Falcon		Great Horned Owl		Grey Hawk					Ontario, Zacate	Kabini	Steppe Eagle, Crowned Eagle, LX-Family		Prairie Falcon	Banded Kestrel		River Hawk
Released			Aug 2011	Oct 2012	Jun 2013	Jan 2014	2015	Jun 2015	Jun 2016	Oct 2017	Jan 2019	Mar 2020	Jan 2021	Jan 2022	Sep 2022	Jan 2023	Jan 2011	May 2013	Apr 2014	May 2015	Feb 2016	Apr 2019	Jul 2020	Jun 2022	Nov 2022
CPU microarchitecture			K10	Piledriver		Steamroller		Excavator	"Excavator+"[22]	Zen	Zen+	Zen 2	Zen 3	Zen 3+	Zen 4		Bobcat	Jaguar	Puma	Puma+[23]	"Excavator+"	Zen		Zen+	"Zen 2+"
ISA			x86-64 v1	x86-64 v2				x86-64 v3							x86-64 v4		x86-64 v1	x86-64 v2			x86-64 v3
Socket	Desktop	Performance	—N/a												AM5	—N/a	—N/a
		Mainstream	—N/a					AM4						—N/a		—N/a
		Entry	FM1	FM2		FM2+		FM2+[a], AM4	AM4					—N/a
		Basic	—N/a														—N/a	AM1	—N/a			FP5	—N/a
	Other		FS1	FS1+, FP2		FP3		FP4		FP5		FP6		FP7	FL1	FP7 FP7r2 FP8	FT1	FT3	FT3b		FP4	FP5	FT5	FP5	FT6
PCI Express version			2.0			3.0								4.0	5.0	4.0	2.0				3.0
CXL			—N/a														—N/a
Fab. (nm)			GF 32SHP (HKMG SOI)			GF 28SHP (HKMG bulk)				GF 14LPP (FinFET bulk)	GF 12LP (FinFET bulk)	TSMC N7 (FinFET bulk)		TSMC N6 (FinFET bulk)	CCD: TSMC N5 (FinFET bulk) cIOD: TSMC N6 (FinFET bulk)	TSMC 4nm (FinFET bulk)	TSMC N40 (bulk)	TSMC N28 (HKMG bulk)	GF 28SHP (HKMG bulk)			GF 14LPP (FinFET bulk)		GF 12LP (FinFET bulk)	TSMC N6 (FinFET bulk)
Die area (mm2)			228	246		245		245	250	210[24]		156	180	210	CCD: (2x) 70 cIOD: 122	178	75 (+ 28 FCH)	107		?	125	149			~100
Min TDP (W)			35	17				12				10		15	65	35	4.5	4	3.95	10	6			12	8
Max APU TDP (W)			100			95		65						45	170	54	18	25					6	54	15
Max stock APU base clock (GHz)			3	3.8	4.1	4.1		3.7	3.8	3.6	3.7	3.8	4.0	3.3	4.7	4.3	1.75	2.2	2	2.2	3.2	2.6	1.2	3.35	2.8
Max APUs per node[b]			1														1
Max core dies per CPU			1												2	1	1
Max CCX per core die			1									2	1				1
Max cores per CCX			4										8				2	4			2			4
Max CPU[c] cores per APU			4									8			16	8	2	4			2			4
Max threads per CPU core			1							2							1					2
Integer pipeline structure			3+3	2+2						4+2		4+2+1	1+3+3+1+2				1+1+1+1				2+2	4+2			4+2+1
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF
IOMMU[d]			—N/a	v2													v1		v2
BMI1, AES-NI, CLMUL, and F16C																	—N/a
MOVBE			—N/a
AVIC, BMI2, RDRAND, and MWAITX/MONITORX																	—N/a
SME[e], TSME[e], ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing			—N/a														—N/a
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT			—N/a														—N/a
MPK, VAES			—N/a														—N/a
SGX			—N/a														—N/a
FPUs per core			1	0.5						1							1				0.5	1
Pipes per FPU			2														2
FPU pipe width			128-bit									256-bit					80-bit	128-bit							256-bit
CPU instruction set SIMD level			SSE4a[f]	AVX				AVX2							AVX-512		SSSE3	AVX			AVX2
3DNow!			3DNow!+	—N/a													—N/a
PREFETCH/PREFETCHW
GFNI			—N/a														—N/a
AMX			—N/a
FMA4, LWP, TBM, and XOP			—N/a							—N/a							—N/a					—N/a
FMA3
AMD XDNA			—N/a														—N/a
L1 data cache per core (KiB)			64	16				32									32
L1 data cache associativity (ways)			2	4				8									8
L1 instruction caches per core			1	0.5						1							1				0.5	1
Max APU total L1 instruction cache (KiB)			256	128		192				256					512	256	64		128		96	128
L1 instruction cache associativity (ways)			2			3				4		8					2				3	4			8
L2 caches per core			1	0.5						1							1				0.5	1
Max APU total L2 cache (MiB)			4					2				4			16		1	2			1			2
L2 cache associativity (ways)			16							8							16					8
Max on-die L3 cache per CCX (MiB)			—N/a							4			16		32		—N/a						4
Max 3D V-Cache per CCD (MiB)										—N/a					64	—N/a							—N/a
Max total in-CCD L3 cache per APU (MiB)										4		8	16		64								4
Max. total 3D V-Cache per APU (MiB)										—N/a					64	—N/a							—N/a
Max. board L3 cache per APU (MiB)										—N/a													—N/a
Max total L3 cache per APU (MiB)										4		8	16		128								4
APU L3 cache associativity (ways)										16													16
L3 cache scheme										Victim													Victim
Max. L4 cache			—N/a														—N/a
Max stock DRAM support			DDR3-1866		DDR3-2133			DDR3-2133, DDR4-2400	DDR4-2400	DDR4-2933		DDR4-3200, LPDDR4-4266		DDR5-4800, LPDDR5-6400	DDR5-5200	DDR5-5600, LPDDR5x-7500	DDR3L-1333	DDR3L-1600	DDR3L-1866		DDR3-1866, DDR4-2400	DDR4-2400	DDR4-1600	DDR4-3200	LPDDR5-5500
Max DRAM channels per APU			2														1					2	1	2
Max stock DRAM bandwidth (GB/s) per APU			29.866		34.132			38.400		46.932		68.256		102.400	83.200	120.000	10.666	12.800	14.933		19.200	38.400	12.800	51.200	88.000
GPU microarchitecture			TeraScale 2 (VLIW5)	TeraScale 3 (VLIW4)		GCN 2nd gen		GCN 3rd gen		GCN 5th gen[25]				RDNA 2		RDNA 3	TeraScale 2 (VLIW5)	GCN 2nd gen			GCN 3rd gen[25]	GCN 5th gen			RDNA 2
GPU instruction set			TeraScale instruction set			GCN instruction set								RDNA instruction set			TeraScale instruction set	GCN instruction set							RDNA instruction set
Max stock GPU base clock (MHz)			600	800	844	866		1108		1250	1400	2100		2400	400		538	600	?	847	900	1200	600	1300	1900
Max stock GPU base GFLOPS[g]			480	614.4	648.1	886.7		1134.5		1760	1971.2	2150.4		3686.4	102.4		86	?	?	?	345.6	460.8	230.4	1331.2	486.4
3D engine[h]			Up to 400:20:8	Up to 384:24:6		Up to 512:32:8				Up to 704:44:16[26]		Up to 512:32:8		768:48:8	128:8:4		80:8:4	128:8:4			Up to 192:12:8	Up to 192:12:4	192:12:4	Up to 512:?:?	128:?:?
			IOMMUv1			IOMMUv2											IOMMUv1		?		IOMMUv2
Video decoder			UVD 3.0			UVD 4.2		UVD 6.0		VCN 1.0[27]		VCN 2.1[28]	VCN 2.2[28]	VCN 3.1		?	UVD 3.0	UVD 4.0	UVD 4.2		UVD 6.2	VCN 1.0			VCN 3.1
Video encoder			—N/a	VCE 1.0		VCE 2.0		VCE 3.1									—N/a	VCE 2.0			VCE 3.4
AMD Fluid Motion
GPU power saving			PowerPlay	PowerTune													PowerPlay	PowerTune[29]
TrueAudio			—N/a			[30]							?				—N/a
FreeSync						1 2												1 2
HDCP[i]			?			1.4				2.2				2.3			?	1.4				2.2			2.3
PlayReady[i]			—N/a							3.0 not yet							—N/a					3.0 not yet
Supported displays[j]			2–3	2–4				3		3 (desktop) 4 (mobile, embedded)		4					2				3	4		4
/drm/radeon[k][32][33]									—N/a												—N/a
/drm/amdgpu[k][34]			—N/a			[35]											—N/a	[35]

Close

1. [a]

   For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
2. [b]

   A PC would be one node.
3. [c]

   An APU combines a CPU and a GPU. Both have cores.
4. [d]

   Requires firmware support.
5. [e]

   Requires firmware support.
6. [f]

   No SSE4. No SSSE3.
7. [g]

   Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
8. [h]

   Unified shaders : texture mapping units : render output units
9. [i]

   To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
10. [j]

    To feed more than two displays, the additional panels must have native DisplayPort support.^[31] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
11. [k]

    DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

1. [1]

   "RADV conforms to Vulkan 1.0". 2017-10-04.
2. [2]

   "Alex Deucher - AMD's New Unified Open Source Driver". 2014-10-07.
3. [3]

   "Initial amdgpu driver release". 2015-04-20.
4. [4]

   "update on amdgpu and future". 2015-09-17.
5. [5]

   Torvalds, Linus (2016-08-07). "Linux 4.8-rc1".
6. [6]

   "No support for GCN 1.0 hardware, e.g. Tahiti XT". 2018-01-29.
7. [7]

   "AMD Radeon HD 6900 (AMD Cayman) series graphics cards". HWlab. hw-lab.com. December 19, 2010. Archived from the original on August 23, 2022. Retrieved August 23, 2022. New VLIW4 architecture of stream processors allowed to save area of each SIMD by 10%, while performing the same compared to previous VLIW5 architecture
8. [8]

   "GPU Specs Database". TechPowerUp. Retrieved August 23, 2022.
9. [9]

   "NPOT Texture (OpenGL Wiki)". Khronos Group. Retrieved February 10, 2021.
10. [10]

    "OpenGL 4.6 Now Exposed For Old AMD Evergreen & Cayman GPUs On Linux Driver". Retrieved 2025-12-12.
11. [11]

    "Mesamatrix". mesamatrix.net. Retrieved 2025-07-15.
12. [12]

    "Conformant Products". Khronos Group. Retrieved 2024-12-02.
13. [13]

    "radv: add Vulkan 1.4 support". Mesa. Retrieved 2024-12-02.
14. [14]

    "AMD Radeon RX 6800 XT Specs". TechPowerUp. Retrieved January 1, 2021.
15. [15]

    "AMD Launches The Radeon PRO W7500/W7600 RDNA3 GPUs". Phoronix. 3 August 2023. Retrieved 4 September 2023.
16. [16]

    "AMD Radeon Pro 5600M Grafikkarte". TopCPU.net (in German). Retrieved 4 September 2023.
17. [17]

    Killian, Zak (March 22, 2017). "AMD publishes patches for Vega support on Linux". Tech Report. Retrieved March 23, 2017.
18. [18]

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