Chaining (vector processing)
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In computing, chaining is a technique used in vector processors in which vector registers generate interim results which can be used immediately, without additional memory references which reduce computational speed.[1] It is a vector equivalent of the register bypass for scalar operations.[2]
The chaining technique was first used by Seymour Cray in the 80 MHz Cray 1 supercomputer in 1976.[3]
