Draft:Intel 18A

Intel's process delays (2016–2021)

Intel held a significant advantage in transistor density over competing foundries through the mid-2010s, having introduced FinFET transistors at the 22 nm node in 2011, earlier than rivals. However, from roughly 2016, Intel encountered persistent delays in transitioning from its 14 nm generation to 10 nm manufacturing. Defect density on its 10 nm process proved difficult to reduce to commercially viable levels, and Intel shipped its first 10 nm consumer product — Ice Lake — only in 2019, approximately two to three years behind schedule.^[9]

During this period, TSMC advanced its own nodes without comparable delays, and by 2020 had achieved what industry analysts considered an effective process leadership position. Apple Inc. began designing its own M-series processors for Mac computers, manufactured at TSMC, and began shipping the first M-series Mac in November 2020, reducing Intel's presence in the high-margin consumer laptop market.^[10]

Five Nodes in Four Years roadmap

In July 2021, newly appointed Intel CEO Pat Gelsinger announced the IDM 2.0 strategy and the five-nodes-in-four-years plan. The five nodes were:^[1]

• Intel 7 — a 10 nm-class FinFET node used for Alder Lake, Raptor Lake, and Sapphire Rapids processors
• Intel 4 — the first Intel node to use extreme ultraviolet lithography (EUV), used for Meteor Lake client processors and Granite Rapids server processors
• Intel 3 — an enhanced FinFET node used for Xeon 6 server processors and some tiles of Clearwater Forest
• Intel 20A — which introduced RibbonFET and PowerVia; later cancelled for high-volume manufacturing
• Intel 18A — the first node to bring both RibbonFET and PowerVia to commercial production

Intel 20A was cancelled for high-volume production as a cost-cutting measure. The client processors originally planned for 20A, Arrow Lake, were instead manufactured at TSMC. Intel indicated in late 2024 that 18A defect density had already reached below 0.40, the threshold at which moving directly from Intel 3 to 18A was economically justified, eliminating the intermediate 20A ramp.^[11]

Leadership changes

Pat Gelsinger, who launched the 5N4Y roadmap, was removed as CEO in December 2024. Lip-Bu Tan, a former chairman of Cadence Design Systems, was appointed CEO in March 2025. Tan has described 2025 as a year of stabilization and 2026 as an execution year, placing the company's growth inflection point in 2027.^[12]

RibbonFET (gate-all-around transistors)

Intel 18A uses the second generation of RibbonFET, Intel's implementation of gate-all-around transistor (GAA) architecture. In a GAA transistor, the gate material completely wraps around the current-carrying channel on all four sides, providing more precise electrostatic control than the FinFET structures used in earlier nodes, which wrapped the gate on only three sides. The additional gate coverage reduces current leakage and allows transistors to operate reliably at lower supply voltages.^[13]

Intel's RibbonFET uses a ribbon-shaped silicon channel rather than the fin-shaped channel of FinFET. The ribbons are stacked vertically, and the total effective channel width (Weff) can be adjusted by varying the number and width of ribbons in the stack. This provides circuit designers with a range of options for trading off drive current, performance, and power consumption within a single process technology.^[5]

The 18A RibbonFET supports four nanoribbons and eight distinct logic threshold voltages (VTs) — four for NMOS and four for PMOS transistors. This range of threshold voltage options allows designers to select transistors optimized for high performance, low power, or intermediate tradeoffs depending on the requirements of each circuit block.^[13]

Additional improvements in the 18A RibbonFET relative to the first-generation version used in Intel 20A include multiple ribbon widths for both 180H and 160H standard cell libraries, optimized logic power and leakage characteristics through design-technology co-optimization (DTCO), and specialized ribbon widths for SRAM bitcell performance.^[14]

PowerVia (backside power delivery)

PowerVia is Intel's implementation of a backside power delivery network (BSPDN). In conventional chip designs, both logic signal routing and power supply connections share the same set of interconnect layers on the front (device) side of the wafer. As transistor density increases, this shared routing creates congestion that constrains both signal routing and power delivery efficiency, and increases voltage drop (IR drop) across the die.^[15]

PowerVia addresses this by relocating power delivery to the back of the wafer, creating physical separation between signal wiring on the front and power delivery on the back. The separated power path uses dedicated metal layers on the backside optimized for low resistance and high current capacity. Separating the two functions frees additional routing resources on the front side of the die for signal connections, allowing higher routing density and reduced interconnect congestion.^[13]

According to Intel, PowerVia improves standard cell utilization by 5 to 10 percent compared to conventional front-side power routing, and delivers up to 4 percent improvement in ISO-power performance (performance at equal power).^[4] The backside metal layers are also designed for thermal conductivity, which helps manage the increased power density associated with dense GAA transistors.^[13]

PowerVia also reduces inherent resistance (IR) drop across the die by approximately one order of magnitude compared to conventional front-side power delivery, according to technical data Intel presented at the VLSI 2025 symposium.^[5]

Extreme ultraviolet lithography

Intel 18A uses extreme ultraviolet lithography (EUV) for patterning the most critical layers. EUV was first used by Intel in production on Intel 4. The 18A node uses single-pass EUV patterning rather than requiring multiple-patterning EUV steps for the critical metal layers, reducing process complexity and manufacturing cost relative to some approaches used at competing foundries.^[16]

High-numerical aperture EUV (High-NA EUV), using newer ASML equipment capable of finer patterning, is not required for 18A. Intel has stated that High-NA EUV tools are being installed at its Oregon facility in preparation for the successor Intel 14A node.^[17]

Process design kit and ecosystem

Intel released the Intel 18A Process Design Kit (PDK) version 1.0 in July 2024. The PDK provides electronic design automation (EDA) tools and design rule specifications that external customers and Intel's own design teams use to create chip layouts compatible with the 18A manufacturing process.^[18]

Intel has stated that more than 35 ecosystem partners — spanning EDA vendors, intellectual property (IP) providers, design services companies, cloud services, and aerospace and defense suppliers — support the 18A process. Major EDA vendors including Cadence Design Systems, Synopsys, and Siemens EDA have updated their tools and reference flows to support 18A design starts.^[4]

In November 2025, Intel released a PDK for Intel 18A-P, an enhanced variant of the base 18A process targeting external foundry customers with additional performance and power improvements. Intel stated that 18A-P introduces lower threshold voltage and leakage-optimized devices and new fine-grain ribbon widths, while maintaining design rule compatibility with the base 18A process.^[17]

18A-P and 18A-PT variants

Intel has disclosed two derivative variants of 18A targeted at specific customer segments.

Intel 18A-P is an enhanced version of the base 18A process, featuring second-generation RibbonFET with lower threshold voltage options and additional fine-grain ribbon widths. It is intended to offer higher performance per watt than base 18A while maintaining design rule compatibility, allowing customers to migrate designs between the two variants with minimal changes.^[17]

Intel 18A-PT is an extension of 18A-P intended for customers building advanced three-dimensional integrated circuit (3DIC) designs for AI and high-performance computing applications. 18A-PT features an updated back-end metal stack, pass-through TSVs (through-silicon vias), die-to-die TSVs, and an advanced hybrid bonding interface (HBI) enabling fine-pitch connectivity between stacked die. This variant is intended for customers who require chiplet-based architectures that integrate multiple specialized die into a single package.^[17]

Oregon (D1X and D1D, Hillsboro)

Intel's primary site for process development and early production of new nodes is its Ronler Acres campus in Hillsboro, Oregon, which houses the D1X and D1D fabrication facilities. Risk production of Intel 18A began at this site in April 2025, and early engineering samples of both Panther Lake and Clearwater Forest were produced here before volume manufacturing transferred to Arizona.^[19]

Arizona (Fab 52, Chandler)

Fab 52 is Intel's fifth high-volume fabrication facility at its Ocotillo campus in Chandler, Arizona. It is the primary high-volume manufacturing site for Intel 18A and is equipped with extreme ultraviolet lithography tools. Intel describes Fab 52 as the most advanced semiconductor fabrication facility currently operating in the United States.^[3][16]

Fab 52 came online for 18A high-volume production in October 2025. The facility is part of Intel's stated $100 billion commitment to expand its domestic manufacturing operations.^[6] Panther Lake compute tiles began production at Fab 52 in the second half of 2025.^[20]

New Mexico (packaging)

Advanced packaging operations for Intel 18A-based products, including the Foveros 3D stacking process used to assemble Panther Lake and Clearwater Forest chiplets, take place at Intel's facility in Rio Rancho, New Mexico. Panther Lake final assembly involves stacking chiplets produced at multiple facilities into a single package at this site.^[6]

Ohio (future expansion)

Intel announced plans to construct two new fabrication facilities in New Albany, Ohio, as part of what it described as a "Silicon Heartland" initiative. As of early 2026, the Ohio construction timeline has been extended to approximately 2030 amid Intel's broader cost-reduction efforts and uncertainty about external foundry demand.^[12]

CHIPS and Science Act funding

Intel is a recipient of funding under the U.S. CHIPS and Science Act of 2022. The company reached a final agreement with the U.S. Department of Commerce for $7.86 billion in direct grants and approximately $11 billion in loans in late 2024. This funding is intended to support Intel's domestic manufacturing expansion, including Fab 52 and the proposed Ohio facilities.^[20]

Panther Lake (Core Ultra Series 3)

Panther Lake is Intel's consumer laptop processor family built on the 18A node. Branded as Core Ultra Series 3, it was announced at Intel's Technology Tour event in October 2025 and formally launched at CES 2026 in January 2026.^[6]

Panther Lake uses a tile-based (chiplet) design, consistent with Intel's approach since Meteor Lake. The compute tile — containing the CPU cores — is manufactured on Intel 18A. Other tiles in the package use different process nodes: the GPU tile and the platform controller tile use Intel 3, and some low-complexity tiles are manufactured at TSMC. These tiles are assembled using Intel's Foveros 3D packaging technology, which stacks the tiles on a base die using fine-pitch hybrid bonding.^[3]

Intel has stated that Panther Lake delivers "Luna Lake-level power efficiency and Arrow Lake-class performance," referring to the company's current Core Ultra Series 2 product lines. The platform targets AI-capable laptops with up to 180 platform TOPS (tera-operations per second) for neural network inference workloads.^[21]

The first Panther Lake SKU began shipping to OEM partners before the end of 2025, with broad retail availability of laptops beginning in January 2026. Major OEMs including Dell, Lenovo, and Asus announced Panther Lake-based laptop designs at CES 2026.^[7]

Intel announced at CES 2026 that Panther Lake will extend beyond laptop applications to edge computing and robotics platforms, and that an Intel Robotics AI software suite will support 18A-based designs for industrial applications.^[6]

Clearwater Forest (Xeon 6+)

Clearwater Forest is Intel's first 18A-based server processor, branded Xeon 6+. It was introduced at Mobile World Congress in March 2026 and is planned for volume shipment in the first half of 2026.^[7]

Clearwater Forest is an E-core-only design intended for high-density, power-efficient data center workloads. The processor contains up to 288 Darkmont E-cores distributed across 12 compute chiplets. The compute chiplets are manufactured on Intel 18A; the base die, which provides I/O and memory interface functions, is manufactured on Intel 3 using what Intel calls the "Intel 3-T" (thinned) process. The chiplets are integrated using Foveros Direct 3D packaging and lateral connectivity via EMIB.^[7]

Clearwater Forest is designed for hyperscale data centers, cloud service providers, and telecommunications infrastructure operators where core count and power efficiency per rack unit are the primary metrics. Intel has stated that Clearwater Forest delivers a 17 percent improvement in instructions per cycle (IPC) over its predecessor Xeon generation.^[21]

Clearwater Forest is also the first mass-produced processor to combine RibbonFET, PowerVia, and Foveros Direct 3D packaging in a single product, representing the most complete integration of Intel's new manufacturing technologies to date.^[18]

Diamond Rapids

Diamond Rapids is Intel's next-generation high-performance data center processor, planned for production in the second half of 2026. Unlike Clearwater Forest, Diamond Rapids uses Intel's P-core architecture and is designed for workloads that require high single-thread performance. The processor is expected to use an LGA9324 socket and will contain up to 192 P-cores across four compute tiles, all manufactured on Intel 18A.^[12]

Nova Lake

Nova Lake is the successor to Panther Lake in Intel's consumer processor lineup, targeting the enthusiast desktop segment. As of early 2026, Nova Lake has been delayed to 2027. Intel has stated that more than 90 percent of Nova Lake desktop units will be manufactured on TSMC's N2 process rather than Intel 18A, reflecting Intel's decision to outsource higher-volume products while 18A yields and capacity mature.^[12]

Future products

Intel has stated that 18A will serve as the manufacturing foundation for at least three future generations of consumer and server products. The node is also designated for use in programs related to U.S. government secure-enclave computing, where domestically manufactured semiconductors are required.^[8]

TSMC N2

TSMC N2 is TSMC's 2 nm-class process node, which entered high-volume manufacturing in the fourth quarter of 2025. Like Intel 18A, N2 uses gate-all-around transistors — TSMC calls its implementation NanoFET. TSMC's N2 does not include backside power delivery in its base configuration; TSMC's backside power variant, N2P, is planned for later deployment, tentatively in 2026 or 2027.^[23]

In terms of transistor density, TSMC N2 is projected to offer higher high-density logic density (approximately 313 MTr/mm²) compared to Intel 18A (238 MTr/mm²), based on industry reports. Intel's lower density partially reflects different design tradeoffs and the additional space required to implement the backside power delivery infrastructure in 18A.^[23]

Intel's 18A entered production before TSMC N2 reached high-volume status, giving it a technical first-to-market claim for backside power delivery at commercial scale. Whether this translates to a competitive manufacturing advantage depends on factors including yield, capacity, and the pace at which foundry customers tape out designs on each node.^[23]

Samsung SF2

Samsung Foundry's SF2 node, also targeting 2 nm-class performance, uses Samsung's Multi-Bridge Channel FET (MBCFET) gate-all-around implementation. Samsung was the first company to bring GAA transistors to commercial production, having done so with its SF3 (3 nm) process in 2022. SF2 is planned for volume production in 2025 and 2026. Samsung is also developing backside power delivery for future nodes, but it was not implemented in SF2.^[23]

Summary comparison

Direct performance and efficiency comparisons across these nodes are difficult because Intel, TSMC, and Samsung measure and report these figures using different methodologies, test structures, and reference designs. Independent third-party comparisons at equivalent conditions are not available as of early 2026, as none of the nodes had been in commercial production long enough for such analysis to be conducted.

Foundry strategy

Intel Foundry Services (IFS), now operating under the broader Intel Foundry brand, was established as part of the IDM 2.0 strategy to manufacture chips for external customers on Intel's process nodes, competing with TSMC and Samsung Foundry. Intel 18A is the first advanced node at which Intel has sought significant external foundry revenue.^[10]

A fundamental challenge for Intel's foundry business is that, unlike TSMC and Samsung, Intel also designs and sells its own processors that compete directly with many of the companies it hopes to attract as foundry customers. Industry observers have noted that companies such as Nvidia, AMD, Qualcomm, and Broadcom may be reluctant to share proprietary chip designs with a competitor.^[10]

Customer engagements

Intel announced in August 2024 that the first external customer was expected to tape out on Intel 18A in the first half of 2025.^[18] As of March 2026, Intel has stated it has two prospective foundry customers evaluating the 18A node, with firm commitments expected in the second half of 2026 extending into the first half of 2027.^[7]

Intel has publicly disclosed that the world's two largest cloud service providers have announced products using Intel 18A technology, and that nine total external awards for 18A have been announced.^[17] The specific identities of these customers were not publicly confirmed as of March 2026, though reports have indicated interest from Microsoft and Amazon Web Services among others.^[20]

Financial backing

In late 2025, Nvidia and SoftBank Group disclosed equity investments in Intel of approximately $5 billion and $2 billion, respectively. These investments were described as expressions of confidence in Intel's manufacturing capabilities and roadmap rather than commitments to specific foundry engagements.^[20]

Dependency of future nodes

Intel has publicly stated that the decision to proceed with Intel 14A and subsequent leading-edge nodes depends on securing sufficient external foundry commitments. The capital expenditure required to develop and ramp a new process node at full scale is difficult to justify without a customer base beyond Intel's own products. CEO Lip-Bu Tan has indicated that if external foundry revenue does not materialize at scale, Intel may reduce investment in nodes beyond 18A.^[7]

Process leadership claims

Intel has described 18A as representing the return of its process leadership position. Some industry analysts have supported this view, noting that 18A is the first node at commercial production to combine both GAA transistors and backside power delivery. Others have argued that density metrics — where TSMC N2 appears to hold an advantage — are more meaningful for most chip applications than the backside power delivery feature, which benefits power-hungry data center chips more than mobile processors.^[23]

The decision to delay Panther Lake's broad market availability to January 2026 rather than shipping in volume in 2025 was interpreted by some analysts as reflecting a slower-than-planned volume ramp, weakening Intel's claim to have beaten TSMC N2 to market in any commercially meaningful sense.^[23]

U.S. manufacturing significance

Because Intel 18A is manufactured in the United States, it has attracted attention from U.S. policymakers and defense and intelligence community stakeholders who have sought to reduce dependence on non-U.S. sources for advanced semiconductors. Intel has positioned 18A as the only sub-2 nm class node available in North America, and has noted its relevance to programs requiring trusted foundry manufacturing for government applications.^[16]

Harvard Business School professor David Yoffie, a former Intel board member, has suggested that separating Intel's foundry business into an independent company would improve its attractiveness to external customers who are reluctant to share designs with an internal Intel competitor, and would strengthen the United States' position as a home for advanced semiconductor manufacturing.^[10]

Financial impact

Intel's gross margins through 2025 remained well below historical norms, at approximately 34.8 percent for the full year, due to the high costs of ramping the 18A node. Free cash flow for 2025 was approximately negative $4.9 billion. Intel's full-year 2025 revenue was approximately $52.9 billion.^[25]