Draft:Nios V
Processor architecture
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Nios V is a 32-bit embedded processor based on the RISC-V instruction set architecture (ISA) designed specifically for the Altera family of field-programmable gate array (FPGA).
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| Designer | Altera/Intel |
|---|---|
| Bits | 32-bit |
| Design | RISC |
| Type | Load–store |
| Encoding | Variable |
| Branching | Compare-and-branch |
| Endianness | Little |
| Page size | 4 KiB |
| Open | No |
| Registers | |
| General-purpose |
|
| Floating-point |
|
Nios V is a successor to Altera's Nios II embedded processor, which had been the company's embedded processor offering for the previous 2 decades, but was discontinued by Intel in 2023.[1] The migration to the RISC-V ISA transitions Altera's embedded processor offering away from a proprietary ISA to an open architecture with support for industry standard software development and compilation tools.
Nios V CPU family
Nios V is offered in 3 different configurations: Nios V/g (general purpose), Nios V/m (microcontroller), and Nios V/c (compact microcontroller).[2]
Nios V/g
The Nios V/g processor is a general-purpose CPU core based on the RISC-V RV32IMZicsr_Zicbom instruction set (optionally with “F” extension):[3]
- RV32IM(F)Zicsr_Zicbom
- Highest performance Nios V processor
- Supports RTOS embedded system
Nios V/m
Nios V/m is a microcontroller core designed to maintain a balance between performance and FPGA resources and is based on the RV32IZicsr variant of the RISC-V architecture and supports either a pipelined or non-pipelined configuration:[4]
- Balanced for performance and size
- Supports RTOS embedded system
- RV32IZicsr (Pipelined) & RV32IZicsr (Non-Pipelined)
- Pipelined
- Implements RV32IZicsr instruction set.
- Supports five-stages pipelined datapath.
- Non-pipelined
- Implements RV32IZicsr instruction set.
- Supports non-pipelined datapath.
- Pipelined
Nios V/c
The Nios V/c a compact microcontroller core is designed for smallest possible logic utilization in FPGAs, and is based on the RISC-V RV32I instruction set:[5]
- Smallest Nios V processor for non-interrupt-driven control application
- No debug features
- RV32I
Hardware generation process
Nios V hardware designers use the Platform Designer system integration tool, a component of the Quartus Prime FPGA development tools, to configure and generate a Nios V system. The configuration graphical user interface (GUI) allows users to choose the Nios V variant, and to add peripheral and I/O-blocks (timers, memory-controllers, serial interface, etc.) to the embedded system. When the hardware specification is complete, Quartus performs the synthesis, place & route to implement the entire system on the selected FPGA target.