Draft:Rivos
Defunct Semiconductor Company
From Wikipedia, the free encyclopedia
Rivos Inc was an American fabless semiconductor company based in Santa Clara, CA. It developed SoCs featuring a high-performance server-class RISC-V CPU and a CUDA compatible GPU with unified memory and cache coherence between them [1].
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Rivos was founded in 2021 by Puneet Kumar, Mark Hayter, and Belli Kuttanna with Lip-Bu Tan taking credit for bringing them together to start the company [2].
It never launched a product, but Rivos did tapeout an SoC on a TSMC 3 nm process and had IP deals with Meta before being acquired by them in 2025 [2][3][4]. Rivos was also a prominent member of the RISC-V open source community, being a premier member of RISC-V international[5] with Mark Hayter on the board of directors[6], and a founding member of the RISC-V Software Ecosystem Project[7].
Open Source Contributions
Throughout the duration of the company, Rivos contributed extensively to open source tools like Linux, GCC, Binutils, GDB, LLVM, as well as to the RISC-V International standards body and to the RISC-V Software Ecosystem.
| Extension | Common Name |
|---|---|
| Zalasr[8] | Atomic Load-Acquire and Store-Release Instructions |
| Svrsw60t59b[9] | PTE Reserved for SW bits 60:59 |
| Smctr/Sscctr[10] | Control transfer records |
| Svvptc[11] | Obviating Memory-Management Instructions after Marking PTEs Valid |
| Ssqosid[12] | Capacity and Bandwidth Controller QoS Register Interface |
| Smcntrpmf[13][14] | Cycle & Instret Privilege Mode Filtering |
| Vb[15][16] | B Standard Extension |
| Smcdeleg/Ssccfg[17] | Counter Delegation |
| Smcsrind/Sscsrind[18][19] | Indirect CSR Access |
| Ssqosid[20] | Quality-of-Service |
| Svvptc[11] | Eliding Memory-Management Fences on Making PTEs Valid |
| Svadu[21][22] | Hardware Updating of PTE A/D Bits |
| Zaamo/Zalrsc[23] | Atomic Memory Operations/Load-Reserved/Store-conditional |
| Zabha[24] | Byte and Halfword Atomic Memory Operations |
| Zacas[25][26] | Atomic Compare-and-Swap |
| Zicfiss, Zicfilp[27] | Control Flow Integrity |
| Zimop, Zcmop[28][29] | Maybe-ops |
| IOMMU[30] | IOMMU |
| Zawrs[31][32] | Wait-on-Reservation-Set |
| Vector Crypto[33] | Vector Crypto |
| SBI[34] | Supervisor Binary Interface |
| RAS[35] | RAS Error-record Register Interface |
| ACPI FFH[36] | ACPI Fixed Function Hardware |
Patent Applications
| Patent | ID |
|---|---|
| Flush-on-demand processor instruction trace | US20240078115A1 |
| Voltage glitch detector | WO2025076373A1 |
| Processor performance profiling using trace actions | US20240193070A1 |
| Defectivity redundancy for memory arrays | WO2025054241A1 |
| Fast decoding of compressed data | US20250085852A1 |
| Hardware data prefetchers for processors | WO2025231479A1 |
| Scheduler and table to manage branch divergence | WO2025250820A1 |
| Stream processing for encrypted, integrity and replay-protected memory | WO2024145348A1 |
| Processor with delayed instruction pipeline flush | WO2024137374A1 |
| Error detection or correction using signed parity codes | WO2024124115A1 |
Notable Employees
Bob McNamara (credited with the improved xterm ANSI parser), Kristian Høgsberg Kristensen (Creator of Wayland)[37]. Palmer Dabbelt, one of the original members of the UC Berkeley lab that created RISC-V and RISC-V maintainer of Linux, Binutils, GDB, and QEMU. Tse-Yu Yeh famous for introducing two level branch prediction algorithms[38].