Gracemont (microarchitecture)
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 | |
| General information | |
|---|---|
| Launched | November 4, 2021[1] |
| Marketed by | Intel |
| Designed by | Intel |
| Common manufacturer |
|
| Performance | |
| Max. CPU clock rate | 0.7 GHz to 4.3 GHz |
| Physical specifications | |
| Cores |
|
| Cache | |
| L1 cache | 96 KB per core:
|
| L2 cache | 2 or 4 MB per module |
| L3 cache | 3 MB per module |
| Architecture and classification | |
| Instruction set | x86-64 |
| Extensions | |
| Products, models, variants | |
| Product code names |
|
| History | |
| Predecessor | Tremont |
| Successor | Crestmont |
Gracemont is a microarchitecture for low-power processors used in systems on a chip (SoCs) made by Intel, and is the successor to Tremont. Like its predecessor, it is also implemented as low-power cores in a hybrid design of the Alder Lake, Raptor Lake and Raptor Lake Refresh processors.[2]
Gracemont is the fourth generation out-of-order low-power Atom microarchitecture, built on the Intel 7 manufacturing process.[3]
The Gracemont microarchitecture has the following enhancements over Tremont:[3]
- Level 1 cache per core:
- Eight-way-associative 64 KB instruction cache
- Eight-way-associative 32 KB data cache
- New on-demand instruction-length decoder
- Instruction issue increased to five per clock (from four)
- Instruction retire increased to eight per clock (from seven)
- Execution ports (functional units) there are now 17 (from ten)
- Reorder buffer increased to 256 entries (from 208)
- Improved branch prediction
- Support for AVX, AVX2, FMA3 and AVX-VNNI instructions[4]
- 2 or 4 MB shared L2 cache per 4-core cluster[3]. Alder Lake family has 2 MB. Higher-end Raptor Lake family with Raptor Cove has 4 MB, while Lower-end Raptor Lake family with Golden Cove has 2 MB.
Technology
- System on a chip (SoC) architecture
- 3D tri-gate transistors
- Thermal design power (TDP)
- 10 W desktop processors
- 6 W mobile processors