List of free and open-source EDA software

This is a list of free and open-source EDA software, including software used for electronic design automation (EDA) in integrated circuit (IC), field-programmable gate array (FPGA), printed circuit board (PCB), and electronic-system design. EDA software is used for tasks including schematic capture, circuit simulation, hardware description language processing, logic synthesis, functional verification, static timing analysis, place and route, physical verification, and IC and PCB layout.^[2]^[3]

Many free and open-source EDA tools are designed for a particular stage of the design process and are combined into larger toolchains. For example, OpenROAD Flow Scripts integrates Yosys, OpenROAD, and KLayout into an automated RTL-to-GDSII digital IC design flow.^[4]^[5]

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Name	Target	License	Description
Hammer	ASIC	BSD-3-Clause	Technology-agnostic physical-design framework developed by UC Berkeley for constructing reusable ASIC design flows and interfacing with different EDA tools and process technologies.^[6]
OpenFASoC	Analog and mixed-signal SoC	Apache-2.0	Automated analog and mixed-signal circuit-generation framework that generates physical designs from user specifications using open-source EDA tools.^[7]
OpenLane	ASIC	Apache-2.0	Automated RTL-to-GDSII ASIC implementation infrastructure using tools including Yosys, OpenROAD, Magic, Netgen, and KLayout.^[8]
OpenROAD Flow Scripts	ASIC	BSD-3-Clause	Automated RTL-to-GDSII reference flow integrating Yosys for synthesis, OpenROAD for physical implementation, and KLayout for final layout processing and verification.^[9]
OSS CAD Suite	Digital logic and FPGA	Various	Binary distribution of open-source tools for RTL synthesis, formal verification, simulation, FPGA place and route, programming, and related digital-design tasks.^[10]
SiliconCompiler	ASIC and FPGA	Apache-2.0	Modular hardware build system that orchestrates open-source and proprietary EDA tools for synthesis, simulation, physical design, and verification.^[11]

Name	Base language	Output	License	Description
Amaranth	Python	Verilog	BSD-2-Clause	Hardware-definition language and toolchain for describing synchronous digital logic, simulation, and FPGA or ASIC development.^[12]
Chisel	Scala	SystemVerilog	Apache-2.0	Hardware construction language for creating parameterized digital circuits and reusable hardware generators for ASIC and FPGA designs.^[13]^[14]
Clash	Haskell	VHDL, Verilog, SystemVerilog	BSD-2-Clause	Functional hardware description language and compiler based on Haskell that generates synthesizable HDL for digital circuits.^[15]^[16]
MyHDL	Python	Verilog, VHDL	LGPL-2.1	Python-based hardware description and verification language supporting simulation and conversion to synthesizable Verilog and VHDL.^[17]
PyRTL	Python	Verilog	BSD-3-Clause	Python library for register-transfer level hardware design, simulation, testing, synthesis, and Verilog generation.^[18]
SpinalHDL	Scala	VHDL, Verilog, SystemVerilog	LGPL-3.0 and MIT	Hardware description language and associated tools for generating RTL designs using Scala, with output compatible with standard EDA toolchains.^[19]

Name	Target	License	Description
CIRCT	Hardware compiler infrastructure	Apache-2.0 with LLVM exceptions	LLVM incubator project applying MLIR compiler infrastructure to hardware design, including intermediate representations and transformation tools for digital hardware.^[20]
slang	SystemVerilog	MIT	SystemVerilog compiler and language-services library providing parsing, type checking, linting, abstract syntax trees, and Python bindings.^[21]
Surelog	SystemVerilog	Apache-2.0	SystemVerilog preprocessor, parser, elaborator, and compiler that produces the Universal Hardware Data Model for use by synthesis, simulation, and verification tools.^[22]
Verible	SystemVerilog	Apache-2.0	Suite of SystemVerilog development tools including a parser, formatter, style linter, and language server.^[23]

Name	Target	License	Description
Bambu	ASIC and FPGA	GPL-3.0	High-level synthesis tool in the PandA framework that synthesizes hardware accelerators from C and C++ descriptions.^[24]
Yosys	ASIC and FPGA	ISC	Framework for RTL synthesis with extensive Verilog support and support for synthesizable SystemVerilog.^[25]

Name	Target	License	Description
cocotb	Functional verification	BSD-3-Clause	Python-based coroutine and cosimulation framework for writing hardware testbenches that interact with HDL simulators through interfaces including VPI and VHPI.^[26]
gem5	Computer architecture	BSD 3-Clause	Modular computer-system architecture simulator for system-level architecture and processor microarchitecture research.^[27]^[28]
GHDL	VHDL	GPL-2.0-or-later	VHDL analyzer, compiler, simulator, and experimental synthesis tool supporting multiple revisions of the VHDL standard.^[29]
Icarus Verilog	Verilog and SystemVerilog	GPL-2.0-or-later	Verilog compilation and simulation system supporting preprocessing, elaboration, optimization, simulation, and multiple code-generation targets.^[30]
SymbiYosys	Formal verification	ISC	Front-end for Yosys-based formal hardware verification flows using techniques including bounded model checking and proof engines.^[31]
Verilator	Verilog and SystemVerilog	LGPL-3.0-only or Artistic-2.0	Compiles synthesizable Verilog and SystemVerilog into cycle-accurate C++ or SystemC models for simulation and verification.^[32]

List of free and open-source EDA software

Integrated design flows and frameworks

Hardware description and construction languages

Hardware compiler and HDL development tools

High-level synthesis and logic synthesis

Simulation and verification

Waveform viewers

Memory compilers and generators

FPGA implementation

Physical design and timing analysis

Layout generation and geometry libraries

IC layout and physical verification

Semiconductor device simulation

Analog and mixed-signal design

Printed circuit board design

Electromagnetic and signal-integrity simulation

See also

References

External links

Related Articles

Timelines

Top Qs

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Name	Target	License	Description
OpenCache	Cache	BSD-3-Clause	Custom cache generator that creates synthesizable Verilog cache logic and uses OpenRAM-generated SRAM arrays.^[34]
OpenRAM	SRAM	BSD-3-Clause	Memory compiler that generates SRAM layouts, netlists, timing and power models, placement-and-routing models, and other views for ASIC design.^[35]
OpenROM	ROM	BSD-3-Clause	ROM compiler included with OpenRAM that generates physical ROM designs from binary or hexadecimal data.^[36]
OpenTCAM	TCAM	Apache-2.0	Configurable SRAM-based TCAM compiler capable of generating RTL for FPGA designs and GDSII layouts for ASIC designs using OpenRAM-generated SRAMs.^[37]

Name	Target	License	Description
nextpnr	FPGA	ISC	Vendor-neutral, timing-driven FPGA place-and-route tool supporting multiple FPGA architectures and open bitstream projects.^[38]
Verilog-to-Routing	FPGA	MIT and other permissive licenses	FPGA CAD and architecture-research framework incorporating synthesis, logic optimization, packing, placement, routing, and timing analysis, including the VPR place-and-route tool.^[39]

Name	Target	License	Description
iEDA	ASIC	MulanPSL-2.0	Open-source physical-design infrastructure and toolchain for implementing ASIC netlists through placement, clock-tree synthesis, routing, timing analysis, and GDS generation.^[40]^[41]
OpenROAD	ASIC	BSD-3-Clause	Physical-design application providing stages including floorplanning, placement, clock tree synthesis, routing, and optimization for automated RTL-to-GDSII flows.^[42]
OpenSTA	Static timing analysis	GPL-3.0	Static timing analysis engine supporting industry-standard formats including Liberty, Verilog, SDC, SPEF, and SDF.^[43]
OpenTimer	Static timing analysis	MIT	Parallel and incremental static timing analyzer supporting Liberty, Verilog, SPEF, and SDC design data.^[44]

Name	Target	License	Description
GDSFactory	IC, photonic, analog, quantum, and MEMS layout	MIT	Python-based chip-design framework for generating parametric layouts, routing, simulation interfaces, process design kits, and verification workflows, with output including GDSII and OASIS files.^[45]
Gdstk	GDSII and OASIS layout	BSL-1.0	C++ and Python library for creating and manipulating GDSII and OASIS layouts, including polygon operations, offsets, paths, and hierarchical cells.^[46]
KFactory	IC and photonic layout	MIT	Python layout framework built on the KLayout geometry engine, providing parametric cells, electrical and optical routing, PDK support, netlist extraction, and layout-versus-schematic verification.^[47]
PHIDL	GDSII layout	MIT	Python-based CAD library for creating parameterized GDS layouts, including geometric operations, routing, device ports, and structures for photonic and nanofabrication designs.^[48]^[49]

Name	Target	License	Description
Electric	IC layout and schematic design	GPL-3.0-or-later	Integrated-circuit design system supporting schematic capture, custom IC layout, design-rule checking, layout-versus-schematic verification, simulation, placement, and routing.^[50]
KLayout	IC layout and physical verification	GPL-2.0-or-later	IC layout editor and viewer with scripting and automation facilities used for viewing and manipulating GDSII and other layout formats and for design-rule and layout-versus-schematic verification.^[51]
Magic	VLSI layout	BSD	VLSI layout editor providing layout creation, extraction, routing, and design-rule checking and used by open-source ASIC design flows.^[52]
Netgen	LVS	GPL	Netlist comparison and management tool primarily used for layout-versus-schematic verification of SPICE and Verilog netlists.^[53]

Name	Target	License	Description
Ngspice	Analog and mixed-signal simulation	Modified BSD and compatible licenses	Mixed-level and mixed-signal circuit simulator derived from SPICE3, Cider, and XSPICE and commonly used for SPICE-based circuit simulation.^[55]
Oregano	Schematic capture and circuit simulation	GPL-2.0	Graphical schematic-capture application that performs circuit simulation using engines including Ngspice and Gnucap.^[56]
Qucs-S	Circuit simulation	GPL-2.0	Graphical schematic capture and circuit-simulation frontend supporting simulation engines including Ngspice and Xyce.^[57]
XCircuit	Schematic capture	GPL-2.0	Schematic-capture and circuit-drawing application for creating electronic circuit diagrams and generating circuit netlists.^[58]
Xschem	Schematic capture	GPL-2.0-or-later	Schematic editor for VLSI, ASIC, and analog circuit design with netlist generation for SPICE, VHDL, and Verilog.^[59]
Xyce	Analog circuit simulation	GPL-3.0-or-later	SPICE-compatible parallel electronic circuit simulator developed at Sandia National Laboratories for simulation ranging from desktop systems to large parallel computers.^[60]

Name	Target	License	Description
Fritzing	PCB	GPL-3.0	Electronics design application providing breadboard, schematic, and PCB views and tools for creating PCB layouts.^[61]
Horizon EDA	PCB	GPL-3.0	Integrated PCB design application providing schematic capture, parts and library management, PCB layout, design-rule checking, and manufacturing-output generation.^[62]
KiCad	PCB	GPL-3.0	EDA suite providing schematic capture, PCB layout, circuit simulation, component-library management, and manufacturing-output generation.^[63]
LibrePCB	PCB	GPL-3.0	Cross-platform EDA suite for schematic capture and printed circuit board design.^[64]
pcb-rnd	PCB	GPL-2.0-or-later	Modular printed circuit board layout editor descended from the PCB program associated with the gEDA project.^[65]

Name	Target	License	Description
gerber2ems	PCB signal integrity	Apache-2.0	Python interface that converts PCB manufacturing data into openEMS simulations for analyzing printed-circuit-board traces and signal integrity.^[66]
openEMS	Electromagnetic simulation	GPL-3.0	Three-dimensional electromagnetic field solver using the finite-difference time-domain method for applications including RF and microwave circuits, antennas, and electromagnetic-wave propagation.^[67]