Mostek 5065

Mostek 5065 registers

15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00	(bit position)
Level 1
																Accumulator
PCH				PCL												PC
															L	Link
Level 2
																Accumulator
PCH				PCL												PC
															L	Link
Level 3
																Accumulator
PCH				PCL												PC
														A	L	Aux/Link
Stack Pointer
0	0	0	0	0	0	0	0									Pointer Register

In the early 1970s the idea of a microprocessor being used as the basis for a standalone computer was still not common, and designs of the era generally included features intended to make them easy to use in what today would be known as microcontrollers: processors that are used to control a device like a cash register or gas pump. These systems have to respond quickly to different inputs, which is often accomplished via interrupts. As this is a common operation in these settings, many designs focused on ways to improve interrupt performance or implementation.^[6][7]

In the case of the 5065, this is accomplished by providing three separate sets of registers for the accumulator, program counter and the internal "main link" register, along with the carry flag. On the receipt of an interrupt, the processor completes the current instruction and then points to the selected set of these registers, or as were called, "levels". This allows the system to track three separate sections of code, corresponding to normal operation and two interrupt levels. External devices can raise an interrupt on two pins, INT 1 and INT 2, both of which may be turned on or off in software. So for instance, if INT 2 is enabled and triggered, the processor responds by completing the current instruction, switching to the level 2 registers, and continuing. Normal operation was level 3, which it returns to when a return-from-interrupt instruction was executed.^[8] This makes interrupt servicing very rapid because the state information is being stored automatically in dedicated registers, whereas many designs require this information to be stored out using user-written code that may take multiple cycles to complete.^[9]

The same system can also be used for fast subroutine calls instead of having to store out the register contents.^[8] As the processor state is saved separately, only the return address has to be explicitly written out in code. In this case, the first 256 locations in memory, the zero page, was used as a call stack. For this to work, this area has to be implemented in some form of writable memory. The page can hold up to 128 16-bit addresses, with the current value indicated by the "pointer register", what would be known as the stack pointer on other designs.^[9]

To aid direct memory access (DMA) implementations, the system included a WAIT pin that can be raised by an external device that wants to access to memory. When this signal was received, the processor would continue with the current instruction, including any required reading and writing from memory. When the instruction was complete, it would raise the DMA pin to indicate it was ready and then went into a paused state. The external device would then perform its DMA operations and then drop WAIT when it was finished. The processor would then drop the DMA pin, unpause, and pick up where it left off.^[10]

There were a total of 51 instructions, and 81 opcodes. The instructions come in many formats, but most of them in two-byte opcode-operand pairs. A small number of one-byte instructions were used for things like return-from-subroutine or shift-left, which do not need any additional information.^[8]

Those instructions that used memory (as opposed to registers) use a two-byte format with the opcode in the upper 6 bits of the first byte. The lower 2 bits controlled the type of memory access. The first (bit 1) indicated whether the following 8-bit operand was a direct or indirect address. The second (bit 0) controlled whether the 8-bit value was offset from the current memory page defined by the program counter, or in the zero page. The following operand byte contains an 8 bit address. This means that when using direct addressing, the data has to lie within 256 bytes of the current instruction or within the first 256 bytes of memory. If access to the greater main memory is needed, indirect addressing must be used.^[8]

Indirect addresses use a two-step access pattern. First the processor reads lower 8-bits of the instruction and looks at bit 0 to see which offset to use. It then reads the byte at that location and the following byte, producing a 16-bit value held in a special buffer. It would then read or write the data to that 16-bit location.^[9] This pattern was commonly seen on minicomputers of the era, as it made certain forms of looping over data easy to implement.^[11][b]

The most significant bit of every address stored in memory was used to specify whether it was a direct or indirect address, this left 15-bits for the actual address, allowing up to 32 kB of memory.^[10] Since the address being pointed to by an indirect address might also have its high bit set, indirect addresses can form chains.^[2] This style of multi-level indirect addressing was also seen on minicomputer systems like the IBM 1620, HP 2100 and Data General Nova, but was uncommon for microprocessors.^[2]

For branches, subroutine calls and jumps, a second format is used where the opcode uses the upper 4 bits, and the lower 4 bits along with the 8-bit operand form a 12-bit address. This meant code could only call other code within a 4 KB "block".^[8] There were many other instruction formats for special purposes.^[12]

Input/output is not memory mapped and is handled through special instructions. The upper 4 bits of the opcode holds the I/O instruction (input, output, status, etc.), while the lower 4 bits are a "free field". The program may place any value in these 4 bits and use it as an ad-hoc data field to send instructions to the device. Triggering the instruction resulted in a four-cycle process. In the first cycle the lower 6 bits of the instruction, including the 4 bit free field, are put on the H bus while the value of the accumulator is put on the L bus. The device can then read both to decode its instruction. On the second cycle, if the CPU is to send data to the device for output, the 8-bit value is put on the bus. On the third, any data being sent to the CPU is returned on the bus. The fourth indicates the end of the I/O cycle.^[8]

The main bus is multiplexed, with a total of 16 pins used for both addressing and data. The bus is split into "high" (H) and "low" (L) sides, both 8-bits. During a memory access, the 15-bit address is placed on the high and low sides, and then the data at that location read or written using the L bus only. This meant that memory accesses require two cycles, making it slower than designs with separate (non-multiplexed) address and data busses.^[8]

Built on the PMOS process that was common in the early 1970s, the 5065 requires three voltage supply levels, -12V (VGG), +5V(VSS), -5V (VDD) and ground. It is packaged in a 40-pin DIP, as was common for most processors of the era. The use of the multiplexed bus reduces pin use to the point that five pins were left unconnected.^[10] As is the case for most PMOS designs, an external clock chip is required, in this case the MK5009. There were also plans to release a peripheral interface adaptor (PIA) in late 1975.^[2]

The system was released with an evaluation system, the two-board GEMS-8, short for General Evaluation Microprocessor System. This included the clock driver, 512 bytes of ROM, 1 to 12 kB of RAM, and a UART for use with a computer terminal. The ROM contains the "Program Aid Routine", a small system development tool and debugger utility. The processor board and PAR ROM was $597, the 12k RAM card another $597, or both together were $995. A cross assembler was also available for an unspecified "16-bit minicomputer".^[2]

Clock speeds for the 5065 do not appear in any surviving references. Instruction times are listed as 3 to 16 μsec.^[2] Although the instruction times are cited as 3 to 16 μsec, a 1 MHz clock can be used.^[13]

• Franks, Kirk (16 May 2023), Personal experience designing and building a MK5065 based system, by a former a Mostek engineer
• Sachs, Jason (18 June 2022). "Development of the MOS Technology 6502: A Historical Perspective". Embedded Related.
• Michalopoulos, Demetrios (October 1975). "New Products: Mostek Announces GEMS-8 Microcomputer System". IEEE Computer. doi:10.1109/C-M.1975.218783. S2CID 2862689.
• "Mostek 5065's by the 1000's" (PDF). MicroComputer Digest. Vol. 1, no. 8. February 1975.
• "Mostek Cuts F8 Prices" (PDF). Microcomputer Digest. October 1976.
• Integrated Circuit Guide. Vol. 3. Mostek. 1974.
• Integrated Circuit Guide. Mostek. 1975.
• Nair, B. Somanathan (2002). Digital Electronics And Logic Design. PHI Learning.
• Silva, Mike (18 September 2013). "Introduction to Microcontrollers - Interrupts". Embedded Related.
• "Introduction to Microcontrollers: Interrupt Processing". Renesas.
• "Programming a Loop with Indirect Addressing". Siemens. 29 January 2007.