RP2350

Announced on 8 August 2024, the RP2350 is the second microcontroller designed by Raspberry Pi Ltd, after the RP2040.^[2] The microcontroller is low cost, with the Raspberry Pi Pico 2 being introduced at US$5 and the RP2350 itself costing as little as US$0.80 in bulk. The microcontroller is software-compatible with the RP2040 and can be programmed in assembly, C, C++, Free Pascal, Rust, MicroPython, CircuitPython, and other languages.

The RP2350 comes in four versions, which are identified by the number of cores (2), a numeral loosely correlated to the core type^[3] (3), log₂ of the number of 16 KB RAM blocks (5), log₂ of the number of 128 KB flash storage blocks (0 or 4), and a letter denoting package type (A or B):^[4]

• RP2350A - 30 GPIO in a 7 × 7 mm QFN-60EP (0.4mm pitch) package (EP means exposed pad in center)
• RP2350B - 48 GPIO in a 10 × 10 mm QFN-80EP (0.4mm pitch) package (EP means exposed pad in center)
• RP2354A - same package as RP2350A (above) includes 2 MB QSPI NOR flash
• RP2354B - same package as RP2350B (above) includes 2 MB QSPI NOR flash

Note: inside the "54" IC packages, a NOR flash die is stacked on top of the microcontroller die, then connected to its QSPI bus and first chip select.

At announcement time, seventeen other manufacturers had products expected to be available within a month.^{[citation needed]}

The RP2350 chip is a 5.3-by-5.3-millimetre (0.21 in × 0.21 in) silicon die in either a 7 mm × 7 mm (0.28 in × 0.28 in) QFN-60EP or a 10 mm × 10 mm (0.39 in × 0.39 in) QFN-80EP surface-mount device (SMD) package.^[2]

• Key features:
  • Two different CPU designs sharing the same computer bus and a 150 MHz clock:
    • Dual ARM Cortex-M33F (ARMv8-M instruction set). Includes DSP instructions, single-precision (SP) floating-point instructions, and a simplified double-precision floating-point coprocessor provides add, subtract, multiply, divide, square root.
    • Dual Hazard3 (RISC-V instruction set, RV32IMAC+), an open-source CPU designed by Luke Wren.^[5]
    • Only one or two cores may be used at the same time. In a "normal" setup, the BootROM spins up core 0, which then performs a "core 1 reset" to spin up a core 1 of the same architecture. A core may be swapped for one of a different architecture by manipulating the ARCHSEL register and initiating a core reset. It is possible to access all four cores without power-cycling the rest of the board.^[6]
  • 520 KB SRAM in ten concurrently accessible banks
  • 8 KB of one-time-programmable (OTP) memory
  • QSPI bus controller supports external flash and PSRAM with execute in place (XIP)
    • Optional in-package 2 MB QSPI NOR flash connected to first chip select
  • DMA controller, 16 channel, 4 IRQ
  • AHB crossbar, fully-connected
  • On-chip switched-mode power supply and programmable low-dropout regulator (LDO) to generate core voltage
  • Two on-chip PLLs to generate 48 MHz USB and 150MHz core clocks
  • RP2350A has 30 GPIO pins, of which four can optionally be used as analog inputs, RP2350B has 48 GPIO pins where eight can be used as analog inputs.
  • Optional boot signing with protected OTP storage
  • Hardware SHA-256 accelerator
  • Hardware random number generator (TRNG) based on ARM's TRNG IP block

• Peripherals:
  • One USB 1.1 (LS & FS) controller and PHY, host and device support, 1.5 Mbps (Low Speed) and 12 Mbps (Full Speed).
  • Two UART controllers.
  • Two SPI controllers.
  • One QSPI (quad SPI) controller, supports 1 / 2 / 4-bit SPI transfers, 2 chip selects.
  • Two I²C controllers.
  • One HSTX (high-speed serial transmit) controller, output-only. This is meant for digital video output. Has access to 8 pins at 300 Mb/s per pin (double data rate)
  • 12 PIO (programmable input–output) state machines.
  • 8 (QFN-60) or 12 (QFN-80) units of dual-channel PWM. Each unit can drive two output signals or measure the frequency or duty cycle of an input signal.
  • 4/8-channel 12-bit 500-kSPS SAR ADC, extra channel is connected to internal temperature sensor. QFN-60EP package has 4 channels, QFN-80EP package has 8 channels.

The following is a simplified comparison of the RP2040 and RP2350 microcontroller families.

Feature	RP2040	RP235xA	RP235xB
Package	QFN-56EP	QFN-60EP	QFN-80EP
CPU Cores	2 × ARM Cortex-M0+	2 × ARM Cortex-M33F (w/FPU)
		2 × Hazard3 RISC-V
CPU Clock	200 MHz[7]	150 MHz
SRAM	264 KB, 6 banks	520 KB, 10 banks
Flash	None	None (RP2350), 2 MB (RP2354)
OTP	None	8 KB
GPIO	30	30	48
DMA	12 chan, 2 IRQ	16 chan, 4 IRQ
PIO	2 (8 state machines)	3 (12 state machines)
DAC	16-ch PWM	16-ch PWM	24-ch PWM
ADC	4-chan 12-bit	4-chan 12-bit	8-chan 12-bit
HSTX	None	1, DDR
Cryptographic Engines	None	RNG, SHA-256

The RP2350 chip was released with errata RP2350-E9, documenting a "Latching behaviour on Bank 0 GPIO pull-down resistors", which was later updated to "Increased leakage current on Bank 0 GPIO when pad input is enabled" due to multiple reports from users,^[8] such as developers of the Bus Pirate.

The defect causes pins configured as inputs to source about 120 μA when the input voltage is between logical low and logical high, pulling them to about 2.2V.^[9]

Luke Wren, one of the engineers working on RP2350 has stated that the supplier responsible for the pad circuitry has provided a faulty design. "We didn't modify the pad, we asked the vendor to modify their own pad. There was one particular structure on the RP2040 FT pad that limited its tolerance, but on inspection the modified layout we got back was a completely different circuit."^[10]

The issue was resolved in the A3 and A4 stepping level versions of the chips, announced in July 2025.^[11]

The RP2350 chip integrates security features including Secure Boot (SB) and OTP memory.

The Secure Boot feature relies on the security features of the Cortex-M33F chip such as the Redundancy Coprocessor (RCP: a separate circuit hardened against fault injection, stack smashing, and timing side-channels). As a result, enabling SB causes the RISC-V cores to be disabled.^[12]: 335 The SB code in BootRom allows for checking blocks in the flash memory for cryptographic signatures using a public key stored in the OTP memory. It also includes anti-rollback protection.^[12]

To assess the level of security of their implementation, Raspberry Pi Foundation launched a hacking contest during DEF CON 32 offering US$10,000 to anyone able to read the OTP memory of the RP2350 chip.^[13] After 30 days no vulnerabilities had been submitted, and the foundation doubled the prize and extended the deadline. In January 2025, the foundation announced four winners of the challenges.^[14] Various attacks were performed including secure boot bypass using laser fault injection or read out of the OTP value using a Focused Ion Beam.