SXM (socket)

High-performance computing socket From Wikipedia, the free encyclopedia

SXM (Server PCI Express Module)[1] is a high bandwidth socket solution for connecting Nvidia Compute Accelerators to a system. Each generation of Nvidia Tesla since the P100 models, the DGX computer series, and the HGX board series come with an SXM socket type that provides high bandwidth and power delivery for the GPU daughter cards.[2] Nvidia offers these combinations as an end-user product e.g. in their models of the DGX system series. Current socket generations are SXM for Pascal based GPUs, SXM2 and SXM3 for Volta based GPUs, SXM4 for Ampere based GPUs, and SXM5 for Hopper based GPUs. These sockets are used for specific models of these accelerators, and offer higher performance per card than PCIe equivalents.[2] The DGX-1 system was the first to be equipped with SXM-2 sockets and thus was the first to carry the form factor compatible SXM modules with P100 GPUs and later was unveiled to be capable of allowing upgrading to (or being pre-equipped with) SXM2 modules with V100 GPUs.[3][4]

Computing node of TSUBAME 3.0 supercomputer showing four Nvidia Tesla P100 SXM modules
Bare SXM sockets next to sockets with GPUs installed

Technical details

SXM boards are typically built with four or eight GPU slots, although some solutions such as the Nvidia DGX-2 connect multiple boards to deliver high performance. While third party solutions for SXM boards exist, most systems integrators such as Supermicro use prebuilt Nvidia HGX boards, which come in four or eight socket configurations.[5] This solution greatly lowers the cost and difficulty of SXM based GPU servers, and enables compatibility and reliability across all boards of the same generation.[citation needed]

SXM modules on e.g. HGX boards, particularly recent generations, may have NVLink switches to allow faster GPU-to-GPU communication. This further reduces bottlenecks which would normally be imposed by CPU and PCIe limitations.[2][6] The GPUs on the daughter cards use NVLink as their main communication protocol.[clarification needed] For example, a Hopper-based H100 SXM5 based GPU can use up to 900 GB/s of bandwidth across 18 NVLink 4 channels, with each contributing a 50 GB/s of bandwidth;[7] In contrast, PCIe 5.0 can handle up to 64 GB/s of bandwidth within a x16 slot.[8] This high bandwidth also means that GPUs can share memory over the NVLink bus, allowing an entire HGX board to present to the host system as a single, massive GPU.[9]

Power delivery is also handled by the SXM socket, negating the need for external power cables such as those needed in PCIe equivalent cards. This, combined with the horizontal mounting, allows more efficient cooling mechanisms, which in turn allow SXM-based GPUs to operate at a much higher thermal design power (TDP). The Hopper-based H100, for example, can draw up to 700 W solely from the SXM socket.[10] The lack of cabling also makes assembling and repairing of large systems much easier, and also reduces the number of possible points of failure.[2]

Starting from P100,[11][12][13] to V100,[14] to A100,[15] to H100,[16] to B200[17][18] and to R100;[19] the comparison of accelerators used in DGX:

General & Architecture

More information Model, Architecture ...
Model Architecture Socket GPU Fabrication Process Transistor count

(billion)

Die size

(mm2)

Launched
P100 Pascal SXM/SXM2 GP100 TSMC 16FF+ 15.3 610 Q2 2016
V100 16GB Volta SXM2 GV100 TSMC 12FFN 21.1 815 Q3 2017
V100 32GB SXM3
A100 40GB Ampere SXM4 GA100 TSMC N7 54.2 826 Q1 2020
A100 80GB Q4 2020
H100 Hopper SXM5 GH100 TSMC 4N 80 814 Q3 2022
H200 Q3 2023
B100 Blackwell SXM6 GB100 TSMC 4NP 208 N/A Q4 2024
B200
R100 Rubin SXM7N/a TSMC 3N 338N/a H2 2026
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Cores, Clock & Power

More information Model, Boost clock (MHz) ...
Model Boost clock

(MHz)

#SM Cores

(FP32 CUDA)

Cores

(FP64 excl. tensor)

Cores

(Mixed INT32/FP32)

Cores

(INT32)

TDP

(W)

P100 1480 56 3584 1792N/aN/a 300
V100 16GB 1530 80 5120 2560 N/A 5120 300
V100 32GB 350
A100 40GB 1410 108 6912 3456 6912 N/A 400
A100 80GB
H100 1980 132 16896 4608 16896 N/A 700
H200 1000
B100 N/aN/aN/aN/aN/aN/a 700
B200 N/aN/aN/aN/aN/aN/a 1000
R100 N/aN/aN/aN/aN/aN/a 2300
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Memory & Cache

More information Model, Memory Type (HBM) ...
Model Memory Type

(HBM)

VRAM Size

(GB)

Memory Speed

(Gb/s)

Bus width

(bits)

Bandwidth

(TB/s)

L1 Cache

Per SM (KB)

L1 Cache

Total (KB)

L2 Cache

(KB)

P100 HBM2 16 1.4 4096 0.72 24 1344 4096
V100 16GB HBM2 16 1.75 4096 0.9 128 10240 6144
V100 32GB 32
A100 40GB HBM2 40 2.4 5120 1.52 192 20736 40960
A100 80GB HBM2e 80 3.2
H100 HBM3 80 5.2 5120 3.35 192 25344 51200
H200 HBM3e 141 6.3 6144 4.8
B100 HBM3e 192 8 8192 8 N/A N/A N/A
B200
R100 HBM4N/aN/aN/aN/aN/aN/aN/a
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Compute Performance, Interconnect & Networking

More information Model, FP32 (TFLOPS) ...
Model FP32

(TFLOPS)

FP64

(TFLOPS)

INT8

dense tensor

FP16

dense tensor

bfloat16

dense tensor

TF32

dense tensor

FP64

dense tensor

Interconnect

(NVLink; TB/s)

Networking
P100 10.6 5.3N/a 21.2N/aN/aN/a 0.16 ConnectX-4

(100 Gb/s)

V100 16GB 15.7 7.8 N/A 125 TFLOPS N/A N/A N/A 0.3 ConnectX-5

(100 Gb/s)

V100 32GB
A100 40GB 19.5 9.7 624 TOPS 312 TFLOPS 312 TFLOPS 156 TFLOPS 19.5 TFLOPS 0.6 ConnectX-6

(200 Gb/s)

A100 80GB
H100 67 34 1.98 POPS 990 TFLOPS 990 TFLOPS 495 TFLOPS 67 TFLOPS 0.9 ConnectX-7

(400 Gb/s)

H200
B100 N/aN/a 3.5 POPS 1.98 PFLOPS 1.98 PFLOPS 989 TFLOPS 30 TFLOPS 1.8 ConnectX-7

(400 Gb/s)

B200 N/aN/a 4.5 POPS 2.25 PFLOPS 2.25 PFLOPS 1.2 PFLOPS 40 TFLOPS
R100 N/aN/aN/aN/aN/aN/aN/aN/a ConnectX-9

(1600 Gb/s)

Close

See also

  • Tegra – System on a chip by Nvidia

References

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