Tagged architecture
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In computer science, a tagged architecture is a type of computer architecture where every word of memory constitutes a tagged union, being divided into a number of bits of data, and a tag section that describes the type of the data: how it is to be interpreted, and, if it is a reference, the type of the object that it points to.[1][2][3]
RCA 601
Some early systems use tagging of data in memory but do not have all of the characteristics now considered to be part of tagged architectures.
The RCA 601[4] has a 3-bit tag register and a 3-bit tag for every 24-bit half-word. Every instruction can request a test for equal or unequal tag, and cause a maskable interrupt if the specified match fails. There is no architectural connection between the tag and the contents of the half-word; it is strictly determined by the software.
Burroughs B5000, B5500 and B5700
The Burroughs B5000,[5] B5500[6] and B5700 have 48-bit words with no appended tag field. However, while there are no tag fields for character, instruction or numeric (floating point) words, all of the control word formats include a 3-bit tag.
Burroughs B6500 and successors
The Burroughs B6500 and its successors have a 3-bit tag for every word.