Talk:CPU cache
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 | The content of Tag RAM was merged into CPU cache on 4 November 2016. The former page's history now serves to provide attribution for that content in the latter page, and it must not be deleted as long as the latter page exists. For the discussion at that location, see its talk page. |
| The content of Smart Cache was merged into CPU cache on 28 March 2019. The former page's history now serves to provide attribution for that content in the latter page, and it must not be deleted as long as the latter page exists. For the discussion at that location, see its talk page. |
Merger
Image:Cache,associative-read.png
I find it confusing that the same word (index) denotes both tags in the Tag SRAM and words in the Data SRAM. Index often denotes the part of address used for selecting the whole cache line (Addr[10:6]), which is not the same as the part used for addressing the Data SRAM (Addr[10:2]) as shown in the image.
Usually people draw the index field connected to a decoder which selects the line. The relevant portion of the line is finally extracted by an additional decoder, which is addressed by the offset field of the address.
The detached organization in the image is also fine, but the words "index" in each line seem redundand and confusing.
Perhaps you could attribute Data SRAM entries as word 0, word 1, etc, and the Tag SRAM entries as tag 0, tag 1, etc? — Preceding unsigned comment added by 161.53.65.130 (talk • contribs) 10:47, 17 November 2008 (UTC