Tick–tock model

Every "tick" represented a shrinking of the process technology of the previous microarchitecture (with minor changes, commonly to the caches, and rarely introducing new instructions, as with Broadwell in late 2014) and every "tock" designated a new microarchitecture.^[1] These occurred roughly every year to 18 months.^[1]

Due to the slowing rate of process improvements, in 2014 Intel created a "tock refresh" of a tock in the form of a smaller update to the microarchitecture^[2] not considered a new generation in and of itself. In March 2016, Intel announced in a Form 10-K report that it would always do this in future, deprecating the tick–tock cycle in favor of a three-step process–architecture–optimization model, under which three generations of processors are produced under a single manufacturing process, with the third generation out of three focusing on optimization.^[3]

After introducing the Skylake architecture on a 14 nm process in 2015, its first optimization was Kaby Lake in 2016. Intel then announced a second optimization, Coffee Lake, in 2017^[4] making a total of four generations at 14 nm^[5] before the Palm Cove die shrink to 10 nm in 2018.

• List of Intel CPU microarchitectures
• Speculative execution CPU vulnerabilities